forked from OSchip/llvm-project
580 lines
16 KiB
C++
580 lines
16 KiB
C++
//===-- TargetParser - Parser for target features ---------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise hardware features such as
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// FPU/CPU/ARCH names as well as specific support such as HDIV, etc.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/ARMBuildAttributes.h"
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#include "llvm/Support/TargetParser.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringSwitch.h"
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#include <cctype>
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using namespace llvm;
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using namespace ARM;
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namespace {
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// List of canonical FPU names (use getFPUSynonym) and which architectural
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// features they correspond to (use getFPUFeatures).
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// FIXME: TableGen this.
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// The entries must appear in the order listed in ARM::FPUKind for correct indexing
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struct {
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const char *NameCStr;
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size_t NameLength;
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ARM::FPUKind ID;
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ARM::FPUVersion FPUVersion;
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ARM::NeonSupportLevel NeonSupport;
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ARM::FPURestriction Restriction;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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} FPUNames[] = {
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#define ARM_FPU(NAME, KIND, VERSION, NEON_SUPPORT, RESTRICTION) \
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{ NAME, sizeof(NAME) - 1, KIND, VERSION, NEON_SUPPORT, RESTRICTION },
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#include "llvm/Support/ARMTargetParser.def"
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};
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// List of canonical arch names (use getArchSynonym).
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// This table also provides the build attribute fields for CPU arch
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// and Arch ID, according to the Addenda to the ARM ABI, chapters
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// 2.4 and 2.3.5.2 respectively.
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// FIXME: SubArch values were simplified to fit into the expectations
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// of the triples and are not conforming with their official names.
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// Check to see if the expectation should be changed.
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// FIXME: TableGen this.
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struct {
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const char *NameCStr;
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size_t NameLength;
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ARM::ArchKind ID;
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const char *CPUAttrCStr;
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size_t CPUAttrLength;
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const char *SubArchCStr;
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size_t SubArchLength;
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ARMBuildAttrs::CPUArch ArchAttr; // Arch ID in build attributes.
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unsigned ArchBaseExtensions;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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// CPU class in build attributes.
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StringRef getCPUAttr() const { return StringRef(CPUAttrCStr, CPUAttrLength); }
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// Sub-Arch name.
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StringRef getSubArch() const { return StringRef(SubArchCStr, SubArchLength); }
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} ARCHNames[] = {
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#define ARM_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_BASE_EXT) \
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{NAME, sizeof(NAME) - 1, ID, CPU_ATTR, sizeof(CPU_ATTR) - 1, SUB_ARCH, \
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sizeof(SUB_ARCH) - 1, ARCH_ATTR, ARCH_BASE_EXT},
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#include "llvm/Support/ARMTargetParser.def"
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};
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// List of Arch Extension names.
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// FIXME: TableGen this.
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struct {
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const char *NameCStr;
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size_t NameLength;
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unsigned ID;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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} ARCHExtNames[] = {
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#define ARM_ARCH_EXT_NAME(NAME, ID) { NAME, sizeof(NAME) - 1, ID },
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#include "llvm/Support/ARMTargetParser.def"
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};
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// List of HWDiv names (use getHWDivSynonym) and which architectural
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// features they correspond to (use getHWDivFeatures).
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// FIXME: TableGen this.
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struct {
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const char *NameCStr;
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size_t NameLength;
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unsigned ID;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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} HWDivNames[] = {
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#define ARM_HW_DIV_NAME(NAME, ID) { NAME, sizeof(NAME) - 1, ID },
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#include "llvm/Support/ARMTargetParser.def"
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};
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// List of CPU names and their arches.
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// The same CPU can have multiple arches and can be default on multiple arches.
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// When finding the Arch for a CPU, first-found prevails. Sort them accordingly.
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// When this becomes table-generated, we'd probably need two tables.
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// FIXME: TableGen this.
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struct {
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const char *NameCStr;
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size_t NameLength;
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ARM::ArchKind ArchID;
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bool Default; // is $Name the default CPU for $ArchID ?
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unsigned DefaultExtensions;
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StringRef getName() const { return StringRef(NameCStr, NameLength); }
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} CPUNames[] = {
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#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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{ NAME, sizeof(NAME) - 1, ID, IS_DEFAULT, DEFAULT_EXT },
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#include "llvm/Support/ARMTargetParser.def"
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};
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} // namespace
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// ======================================================= //
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// Information by ID
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// ======================================================= //
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StringRef llvm::ARM::getFPUName(unsigned FPUKind) {
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if (FPUKind >= ARM::FK_LAST)
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return StringRef();
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return FPUNames[FPUKind].getName();
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}
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unsigned llvm::ARM::getFPUVersion(unsigned FPUKind) {
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if (FPUKind >= ARM::FK_LAST)
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return 0;
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return FPUNames[FPUKind].FPUVersion;
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}
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unsigned llvm::ARM::getFPUNeonSupportLevel(unsigned FPUKind) {
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if (FPUKind >= ARM::FK_LAST)
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return 0;
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return FPUNames[FPUKind].NeonSupport;
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}
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unsigned llvm::ARM::getFPURestriction(unsigned FPUKind) {
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if (FPUKind >= ARM::FK_LAST)
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return 0;
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return FPUNames[FPUKind].Restriction;
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}
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unsigned llvm::ARM::getDefaultFPU(StringRef CPU) {
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return StringSwitch<unsigned>(CPU)
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#define ARM_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT) \
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.Case(NAME, DEFAULT_FPU)
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#include "llvm/Support/ARMTargetParser.def"
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.Default(ARM::FK_INVALID);
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}
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bool llvm::ARM::getHWDivFeatures(unsigned HWDivKind,
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std::vector<const char *> &Features) {
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if (HWDivKind == ARM::AEK_INVALID)
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return false;
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if (HWDivKind & ARM::AEK_HWDIVARM)
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Features.push_back("+hwdiv-arm");
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else
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Features.push_back("-hwdiv-arm");
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if (HWDivKind & ARM::AEK_HWDIV)
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Features.push_back("+hwdiv");
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else
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Features.push_back("-hwdiv");
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return true;
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}
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bool llvm::ARM::getExtensionFeatures(unsigned Extensions,
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std::vector<const char *> &Features) {
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if (Extensions == ARM::AEK_INVALID)
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return false;
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if (Extensions & ARM::AEK_CRC)
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Features.push_back("+crc");
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else
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Features.push_back("-crc");
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if (Extensions & ARM::AEK_DSP)
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Features.push_back("+dsp");
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else
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Features.push_back("-dsp");
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return getHWDivFeatures(Extensions, Features);
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}
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bool llvm::ARM::getFPUFeatures(unsigned FPUKind,
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std::vector<const char *> &Features) {
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if (FPUKind >= ARM::FK_LAST || FPUKind == ARM::FK_INVALID)
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return false;
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// fp-only-sp and d16 subtarget features are independent of each other, so we
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// must enable/disable both.
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switch (FPUNames[FPUKind].Restriction) {
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case ARM::FR_SP_D16:
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Features.push_back("+fp-only-sp");
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Features.push_back("+d16");
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break;
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case ARM::FR_D16:
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Features.push_back("-fp-only-sp");
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Features.push_back("+d16");
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break;
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case ARM::FR_None:
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Features.push_back("-fp-only-sp");
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Features.push_back("-d16");
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break;
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}
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// FPU version subtarget features are inclusive of lower-numbered ones, so
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// enable the one corresponding to this version and disable all that are
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// higher. We also have to make sure to disable fp16 when vfp4 is disabled,
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// as +vfp4 implies +fp16 but -vfp4 does not imply -fp16.
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switch (FPUNames[FPUKind].FPUVersion) {
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case ARM::FV_VFPV5:
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Features.push_back("+fp-armv8");
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break;
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case ARM::FV_VFPV4:
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Features.push_back("+vfp4");
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Features.push_back("-fp-armv8");
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break;
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case ARM::FV_VFPV3_FP16:
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Features.push_back("+vfp3");
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Features.push_back("+fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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case ARM::FV_VFPV3:
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Features.push_back("+vfp3");
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Features.push_back("-fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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case ARM::FV_VFPV2:
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Features.push_back("+vfp2");
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Features.push_back("-vfp3");
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Features.push_back("-fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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case ARM::FV_NONE:
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Features.push_back("-vfp2");
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Features.push_back("-vfp3");
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Features.push_back("-fp16");
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Features.push_back("-vfp4");
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Features.push_back("-fp-armv8");
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break;
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}
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// crypto includes neon, so we handle this similarly to FPU version.
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switch (FPUNames[FPUKind].NeonSupport) {
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case ARM::NS_Crypto:
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Features.push_back("+neon");
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Features.push_back("+crypto");
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break;
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case ARM::NS_Neon:
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Features.push_back("+neon");
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Features.push_back("-crypto");
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break;
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case ARM::NS_None:
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Features.push_back("-neon");
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Features.push_back("-crypto");
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break;
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}
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return true;
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}
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StringRef llvm::ARM::getArchName(unsigned ArchKind) {
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if (ArchKind >= ARM::AK_LAST)
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return StringRef();
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return ARCHNames[ArchKind].getName();
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}
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StringRef llvm::ARM::getCPUAttr(unsigned ArchKind) {
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if (ArchKind >= ARM::AK_LAST)
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return StringRef();
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return ARCHNames[ArchKind].getCPUAttr();
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}
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StringRef llvm::ARM::getSubArch(unsigned ArchKind) {
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if (ArchKind >= ARM::AK_LAST)
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return StringRef();
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return ARCHNames[ArchKind].getSubArch();
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}
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unsigned llvm::ARM::getArchAttr(unsigned ArchKind) {
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if (ArchKind >= ARM::AK_LAST)
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return ARMBuildAttrs::CPUArch::Pre_v4;
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return ARCHNames[ArchKind].ArchAttr;
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}
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StringRef llvm::ARM::getArchExtName(unsigned ArchExtKind) {
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for (const auto AE : ARCHExtNames) {
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if (ArchExtKind == AE.ID)
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return AE.getName();
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}
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return StringRef();
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}
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StringRef llvm::ARM::getHWDivName(unsigned HWDivKind) {
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for (const auto D : HWDivNames) {
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if (HWDivKind == D.ID)
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return D.getName();
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}
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return StringRef();
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}
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unsigned llvm::ARM::getDefaultExtensions(StringRef CPU) {
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for (const auto C : CPUNames) {
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if (CPU == C.getName())
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return (ARCHNames[C.ArchID].ArchBaseExtensions | C.DefaultExtensions);
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}
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return ARM::AEK_INVALID;
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}
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StringRef llvm::ARM::getDefaultCPU(StringRef Arch) {
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unsigned AK = parseArch(Arch);
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if (AK == ARM::AK_INVALID)
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return StringRef();
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// Look for multiple AKs to find the default for pair AK+Name.
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for (const auto CPU : CPUNames) {
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if (CPU.ArchID == AK && CPU.Default)
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return CPU.getName();
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}
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return StringRef();
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}
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// ======================================================= //
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// Parsers
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// ======================================================= //
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static StringRef getHWDivSynonym(StringRef HWDiv) {
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return StringSwitch<StringRef>(HWDiv)
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.Case("thumb,arm", "arm,thumb")
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.Default(HWDiv);
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}
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static StringRef getFPUSynonym(StringRef FPU) {
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return StringSwitch<StringRef>(FPU)
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.Cases("fpa", "fpe2", "fpe3", "maverick", "invalid") // Unsupported
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.Case("vfp2", "vfpv2")
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.Case("vfp3", "vfpv3")
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.Case("vfp4", "vfpv4")
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.Case("vfp3-d16", "vfpv3-d16")
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.Case("vfp4-d16", "vfpv4-d16")
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.Cases("fp4-sp-d16", "vfpv4-sp-d16", "fpv4-sp-d16")
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.Cases("fp4-dp-d16", "fpv4-dp-d16", "vfpv4-d16")
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.Case("fp5-sp-d16", "fpv5-sp-d16")
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.Cases("fp5-dp-d16", "fpv5-dp-d16", "fpv5-d16")
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// FIXME: Clang uses it, but it's bogus, since neon defaults to vfpv3.
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.Case("neon-vfpv3", "neon")
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.Default(FPU);
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}
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static StringRef getArchSynonym(StringRef Arch) {
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return StringSwitch<StringRef>(Arch)
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.Case("v6sm", "v6s-m")
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.Case("v6m", "v6-m")
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.Case("v7a", "v7-a")
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.Case("v7r", "v7-r")
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.Case("v7m", "v7-m")
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.Case("v7em", "v7e-m")
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.Cases("v8", "v8a", "aarch64", "arm64", "v8-a")
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.Case("v8.1a", "v8.1-a")
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.Default(Arch);
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}
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// MArch is expected to be of the form (arm|thumb)?(eb)?(v.+)?(eb)?, but
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// (iwmmxt|xscale)(eb)? is also permitted. If the former, return
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// "v.+", if the latter, return unmodified string, minus 'eb'.
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// If invalid, return empty string.
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StringRef llvm::ARM::getCanonicalArchName(StringRef Arch) {
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size_t offset = StringRef::npos;
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StringRef A = Arch;
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StringRef Error = "";
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// Begins with "arm" / "thumb", move past it.
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if (A.startswith("arm64"))
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offset = 5;
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else if (A.startswith("arm"))
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offset = 3;
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else if (A.startswith("thumb"))
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offset = 5;
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else if (A.startswith("aarch64")) {
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offset = 7;
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// AArch64 uses "_be", not "eb" suffix.
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if (A.find("eb") != StringRef::npos)
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return Error;
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if (A.substr(offset, 3) == "_be")
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offset += 3;
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}
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// Ex. "armebv7", move past the "eb".
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if (offset != StringRef::npos && A.substr(offset, 2) == "eb")
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offset += 2;
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// Or, if it ends with eb ("armv7eb"), chop it off.
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else if (A.endswith("eb"))
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A = A.substr(0, A.size() - 2);
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// Trim the head
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if (offset != StringRef::npos)
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A = A.substr(offset);
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// Empty string means offset reached the end, which means it's valid.
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if (A.empty())
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return Arch;
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// Only match non-marketing names
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if (offset != StringRef::npos) {
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// Must start with 'vN'.
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if (A[0] != 'v' || !std::isdigit(A[1]))
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return Error;
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// Can't have an extra 'eb'.
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if (A.find("eb") != StringRef::npos)
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return Error;
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}
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// Arch will either be a 'v' name (v7a) or a marketing name (xscale).
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return A;
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}
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unsigned llvm::ARM::parseHWDiv(StringRef HWDiv) {
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StringRef Syn = getHWDivSynonym(HWDiv);
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for (const auto D : HWDivNames) {
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if (Syn == D.getName())
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return D.ID;
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}
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return ARM::AEK_INVALID;
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}
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unsigned llvm::ARM::parseFPU(StringRef FPU) {
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StringRef Syn = getFPUSynonym(FPU);
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for (const auto F : FPUNames) {
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if (Syn == F.getName())
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return F.ID;
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}
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return ARM::FK_INVALID;
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}
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// Allows partial match, ex. "v7a" matches "armv7a".
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unsigned llvm::ARM::parseArch(StringRef Arch) {
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Arch = getCanonicalArchName(Arch);
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StringRef Syn = getArchSynonym(Arch);
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for (const auto A : ARCHNames) {
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if (A.getName().endswith(Syn))
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return A.ID;
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}
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return ARM::AK_INVALID;
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}
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unsigned llvm::ARM::parseArchExt(StringRef ArchExt) {
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for (const auto A : ARCHExtNames) {
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if (ArchExt == A.getName())
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return A.ID;
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}
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return ARM::AEK_INVALID;
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}
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unsigned llvm::ARM::parseCPUArch(StringRef CPU) {
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for (const auto C : CPUNames) {
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if (CPU == C.getName())
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return C.ArchID;
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}
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return ARM::AK_INVALID;
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}
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// ARM, Thumb, AArch64
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unsigned llvm::ARM::parseArchISA(StringRef Arch) {
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return StringSwitch<unsigned>(Arch)
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.StartsWith("aarch64", ARM::IK_AARCH64)
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.StartsWith("arm64", ARM::IK_AARCH64)
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.StartsWith("thumb", ARM::IK_THUMB)
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.StartsWith("arm", ARM::IK_ARM)
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.Default(ARM::EK_INVALID);
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}
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// Little/Big endian
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unsigned llvm::ARM::parseArchEndian(StringRef Arch) {
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if (Arch.startswith("armeb") || Arch.startswith("thumbeb") ||
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Arch.startswith("aarch64_be"))
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return ARM::EK_BIG;
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if (Arch.startswith("arm") || Arch.startswith("thumb")) {
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if (Arch.endswith("eb"))
|
|
return ARM::EK_BIG;
|
|
else
|
|
return ARM::EK_LITTLE;
|
|
}
|
|
|
|
if (Arch.startswith("aarch64"))
|
|
return ARM::EK_LITTLE;
|
|
|
|
return ARM::EK_INVALID;
|
|
}
|
|
|
|
// Profile A/R/M
|
|
unsigned llvm::ARM::parseArchProfile(StringRef Arch) {
|
|
Arch = getCanonicalArchName(Arch);
|
|
switch (parseArch(Arch)) {
|
|
case ARM::AK_ARMV6M:
|
|
case ARM::AK_ARMV7M:
|
|
case ARM::AK_ARMV6SM:
|
|
case ARM::AK_ARMV7EM:
|
|
return ARM::PK_M;
|
|
case ARM::AK_ARMV7R:
|
|
return ARM::PK_R;
|
|
case ARM::AK_ARMV7:
|
|
case ARM::AK_ARMV7A:
|
|
case ARM::AK_ARMV7K:
|
|
case ARM::AK_ARMV7L:
|
|
case ARM::AK_ARMV8A:
|
|
case ARM::AK_ARMV8_1A:
|
|
return ARM::PK_A;
|
|
}
|
|
return ARM::PK_INVALID;
|
|
}
|
|
|
|
// Version number (ex. v7 = 7).
|
|
unsigned llvm::ARM::parseArchVersion(StringRef Arch) {
|
|
Arch = getCanonicalArchName(Arch);
|
|
switch (parseArch(Arch)) {
|
|
case ARM::AK_ARMV2:
|
|
case ARM::AK_ARMV2A:
|
|
return 2;
|
|
case ARM::AK_ARMV3:
|
|
case ARM::AK_ARMV3M:
|
|
return 3;
|
|
case ARM::AK_ARMV4:
|
|
case ARM::AK_ARMV4T:
|
|
return 4;
|
|
case ARM::AK_ARMV5:
|
|
case ARM::AK_ARMV5T:
|
|
case ARM::AK_ARMV5TE:
|
|
case ARM::AK_IWMMXT:
|
|
case ARM::AK_IWMMXT2:
|
|
case ARM::AK_XSCALE:
|
|
case ARM::AK_ARMV5E:
|
|
case ARM::AK_ARMV5TEJ:
|
|
return 5;
|
|
case ARM::AK_ARMV6:
|
|
case ARM::AK_ARMV6J:
|
|
case ARM::AK_ARMV6K:
|
|
case ARM::AK_ARMV6T2:
|
|
case ARM::AK_ARMV6Z:
|
|
case ARM::AK_ARMV6ZK:
|
|
case ARM::AK_ARMV6M:
|
|
case ARM::AK_ARMV6SM:
|
|
case ARM::AK_ARMV6HL:
|
|
return 6;
|
|
case ARM::AK_ARMV7:
|
|
case ARM::AK_ARMV7A:
|
|
case ARM::AK_ARMV7R:
|
|
case ARM::AK_ARMV7M:
|
|
case ARM::AK_ARMV7L:
|
|
case ARM::AK_ARMV7HL:
|
|
case ARM::AK_ARMV7S:
|
|
case ARM::AK_ARMV7EM:
|
|
case ARM::AK_ARMV7K:
|
|
return 7;
|
|
case ARM::AK_ARMV8A:
|
|
case ARM::AK_ARMV8_1A:
|
|
return 8;
|
|
}
|
|
return 0;
|
|
}
|