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AArch64
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[GlobalMerge] Take into account minsize on Global users' parents.
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2015-06-04 20:39:23 +00:00 |
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ARM
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[ARM] Add support for -sp- FPUs and FPU none to TargetParser
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2015-06-05 13:31:19 +00:00 |
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BPF
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[bpf] add big- and host- endian support
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2015-06-04 19:15:05 +00:00 |
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CPP
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[opaque pointer type] Add textual IR support for explicit type parameter to the call instruction
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2015-04-16 23:24:18 +00:00 |
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Generic
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Resubmit r237954 (MIR Serialization: print and parse LLVM IR using MIR format).
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2015-05-27 18:02:19 +00:00 |
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Hexagon
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[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.
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2015-06-05 16:00:11 +00:00 |
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Inputs
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IR: Give 'DI' prefix to debug info metadata
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2015-04-29 16:38:44 +00:00 |
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MIR
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MIR Serialization: use correct line and column numbers for LLVM IR errors.
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2015-05-29 17:05:41 +00:00 |
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MSP430
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[opaque pointer type] Add textual IR support for explicit type parameter to gep operator
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2015-03-13 18:20:45 +00:00 |
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Mips
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[mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.
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2015-06-02 20:32:50 +00:00 |
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NVPTX
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[NVPTX] roll forward r239082
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2015-06-04 21:28:26 +00:00 |
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PowerPC
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Add support for VSX FMA single-precision instructions to the PPC back end
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2015-05-29 17:13:25 +00:00 |
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R600
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R600/SI: Reimplement isLegalAddressingMode
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2015-06-04 16:17:42 +00:00 |
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SPARC
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Add support for the Sparc implementation-defined "ASR" registers.
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2015-05-18 16:29:48 +00:00 |
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SystemZ
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[DAGCombiner] Account for getVectorIdxTy() when narrowing vector load
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2015-05-05 19:34:10 +00:00 |
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Thumb
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Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM.
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2015-05-28 20:02:45 +00:00 |
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Thumb2
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ARM: Thumb2 LDRD/STRD supports independent input/output regs
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2015-06-03 16:30:24 +00:00 |
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WinEH
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[WinEH] C++ EH state numbering fixes
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2015-05-20 23:22:24 +00:00 |
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X86
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[X86][AVX2] Added tests for v32i8 vector shifts
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2015-06-05 12:35:36 +00:00 |
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XCore
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IR: Give 'DI' prefix to debug info metadata
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2015-04-29 16:38:44 +00:00 |
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