llvm-project/llvm/lib/CodeGen
Chris Lattner b25de3ff60 eliminate the "Value" printing methods that print to a std::ostream.
This required converting a bunch of stuff off DOUT and other cleanups.

llvm-svn: 79819
2009-08-23 04:37:46 +00:00
..
AsmPrinter convert the DIE printing stuff to use raw_ostream instead of std::ostream. 2009-08-23 01:01:17 +00:00
PBQP Remove <iostream>. 2009-08-15 22:28:08 +00:00
SelectionDAG Add check for completeness. Note that this doesn't actually have any 2009-08-23 00:14:19 +00:00
BranchFolding.cpp Convert DOUT to DEBUG(errs()...). 2009-08-22 20:03:00 +00:00
CMakeLists.txt fix a gone file. 2009-08-23 01:11:21 +00:00
CodePlacementOpt.cpp Fix CodePlacementOpt::OptimizeIntraLoopEdges so that its return value 2009-05-18 21:02:18 +00:00
DeadMachineInstructionElim.cpp Convert DOUT to DEBUG(errs()...). 2009-08-22 20:04:03 +00:00
DwarfEHPrepare.cpp Push LLVMContexts through the IntegerType APIs. 2009-08-13 21:58:54 +00:00
ELF.h Remove hack used to strip unwanted chars from section name 2009-08-13 21:25:27 +00:00
ELFCodeEmitter.cpp Rename TargetAsmInfo (and its subclasses) to MCAsmInfo. 2009-08-22 20:48:53 +00:00
ELFCodeEmitter.h Change ELFCodeEmitter logic to emit the constant pool and jump tables to 2009-07-21 23:13:26 +00:00
ELFWriter.cpp rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
ELFWriter.h rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
ExactHazardRecognizer.cpp Normalize how the 'namespace llvm {' is used in this file. 2009-08-22 20:08:44 +00:00
ExactHazardRecognizer.h Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets. 2009-08-10 15:55:25 +00:00
GCMetadata.cpp remove std::ostream versions of printing stuff for MBB and MF, 2009-08-23 03:13:20 +00:00
GCMetadataPrinter.cpp rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
GCStrategy.cpp llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. 2009-07-14 16:55:14 +00:00
IfConversion.cpp remove various std::ostream version of printing methods from 2009-08-23 03:41:05 +00:00
IntrinsicLowering.cpp Push LLVMContexts through the IntegerType APIs. 2009-08-13 21:58:54 +00:00
LLVMTargetMachine.cpp remove std::ostream versions of printing stuff for MBB and MF, 2009-08-23 03:13:20 +00:00
LatencyPriorityQueue.cpp Add initial support for back-scheduling address computations, 2008-12-16 03:35:01 +00:00
LazyLiveness.cpp Add missing includes. 2009-08-19 22:05:21 +00:00
LiveInterval.cpp shoot a few more std::ostream print methods in the head. 2009-08-23 03:47:42 +00:00
LiveIntervalAnalysis.cpp remove various std::ostream version of printing methods from 2009-08-23 03:41:05 +00:00
LiveStackAnalysis.cpp shoot a few more std::ostream print methods in the head. 2009-08-23 03:47:42 +00:00
LiveVariables.cpp remove various std::ostream version of printing methods from 2009-08-23 03:41:05 +00:00
LowerSubregs.cpp Convert DOUT to DEBUG(errs()...). 2009-08-22 20:23:49 +00:00
MachO.h rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
MachOCodeEmitter.cpp rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
MachOCodeEmitter.h rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
MachOWriter.cpp eliminate the "Value" printing methods that print to a std::ostream. 2009-08-23 04:37:46 +00:00
MachOWriter.h rename TAI -> MAI, being careful not to make MAILJMP instructions :) 2009-08-22 21:43:10 +00:00
MachineBasicBlock.cpp remove std::ostream versions of printing stuff for MBB and MF, 2009-08-23 03:13:20 +00:00
MachineDominators.cpp Eliminate several more unnecessary intptr_t casts. 2009-02-18 05:09:16 +00:00
MachineFunction.cpp remove std::ostream versions of printing stuff for MBB and MF, 2009-08-23 03:13:20 +00:00
MachineFunctionAnalysis.cpp Give MachineFunctionAnalysis a destructor so it can verify that 2009-08-01 04:19:43 +00:00
MachineFunctionPass.cpp Reapply r77654 with a fix: MachineFunctionPass's getAnalysisUsage 2009-07-31 18:16:33 +00:00
MachineInstr.cpp remove various std::ostream version of printing methods from 2009-08-23 03:41:05 +00:00
MachineLICM.cpp Convert DOUT to DEBUG(errs()...). 2009-08-22 20:25:44 +00:00
MachineLoopInfo.cpp Reapply r77654 with a fix: MachineFunctionPass's getAnalysisUsage 2009-07-31 18:16:33 +00:00
MachineModuleInfo.cpp Use setPreservesAll and setPreservesCFG in CodeGen passes. 2009-07-31 23:37:33 +00:00
MachinePassRegistry.cpp Remove attribution from file headers, per discussion on llvmdev. 2007-12-29 20:36:04 +00:00
MachineRegisterInfo.cpp Part 1. 2009-06-15 08:28:29 +00:00
MachineSink.cpp remove std::ostream versions of printing stuff for MBB and MF, 2009-08-23 03:13:20 +00:00
MachineVerifier.cpp remove various std::ostream version of printing methods from 2009-08-23 03:41:05 +00:00
Makefile Removed trailing whitespace from Makefiles. 2009-01-09 16:44:42 +00:00
ObjectCodeEmitter.cpp Remove accidental commited comment 2009-08-05 07:00:43 +00:00
OcamlGC.cpp Registry.h should not depend on CommandLine.h. 2009-01-16 07:02:28 +00:00
PHIElimination.cpp Use setPreservesAll and setPreservesCFG in CodeGen passes. 2009-07-31 23:37:33 +00:00
PHIElimination.h Added PHI Def & Kill tracking to PHIElimination pass. 2009-07-23 04:34:03 +00:00
Passes.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
PostRASchedulerList.cpp Fix counting of Post-RA scheduling stalls. Improve debug output. 2009-08-12 21:47:46 +00:00
PreAllocSplitting.cpp Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg. 2009-08-10 23:43:28 +00:00
PrologEpilogInserter.cpp Record variable debug info at ISel time directly. 2009-08-22 17:12:53 +00:00
PrologEpilogInserter.h Scan for presence of calls and determine max callframe size early. To allow ProcessFunctionBeforeCalleeSaveScan() use this information 2009-07-16 13:50:40 +00:00
PseudoSourceValue.cpp Push LLVMContexts through the IntegerType APIs. 2009-08-13 21:58:54 +00:00
README.txt Remove tabs. 2008-08-22 00:04:26 +00:00
RegAllocLinearScan.cpp Convert DOUT to DEBUG(errs()...). 2009-08-22 20:30:53 +00:00
RegAllocLocal.cpp Convert DOUT to DEBUG(errs()...). 2009-08-22 20:38:09 +00:00
RegAllocPBQP.cpp Suppress build warning in -Asserts 2009-08-20 20:01:34 +00:00
RegAllocSimple.cpp Convert DOUT to DEBUG(errs()...). 2009-08-22 20:40:21 +00:00
RegisterCoalescer.cpp Clean up the use of static and anonymous namespaces. This turned up 2008-05-13 00:00:25 +00:00
RegisterScavenging.cpp Simplify RegScavenger::FindUnusedReg. 2009-08-18 21:14:54 +00:00
ScheduleDAG.cpp Convert DOUT to DEBUG(errs()...). 2009-08-22 20:41:06 +00:00
ScheduleDAGEmit.cpp When scheduling a block in parts, keep track of the overall 2009-02-11 04:27:20 +00:00
ScheduleDAGInstrs.cpp Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling. 2009-08-19 16:08:58 +00:00
ScheduleDAGInstrs.h Use the schedule itinerary operand use/def cycle information to adjust dependence edge latency for post-RA scheduling. 2009-08-19 16:08:58 +00:00
ScheduleDAGPrinter.cpp Switch to getNameStr(). 2009-07-24 08:24:36 +00:00
ShadowStackGC.cpp Actually privatize a IntegerTypes, and fix a few bugs exposed by this. 2009-08-13 23:27:32 +00:00
ShrinkWrapping.cpp Convert DOUT to DEBUG(errs()...). 2009-08-22 20:46:59 +00:00
SimpleHazardRecognizer.h Post RA scheduler changes. Introduce a hazard recognizer that uses the target schedule information to accurately model the pipeline. Update the scheduler to correctly handle multi-issue targets. 2009-08-10 15:55:25 +00:00
SimpleRegisterCoalescing.cpp Convert DOUT to DEBUG(errs()...). 2009-08-22 20:52:46 +00:00
SimpleRegisterCoalescing.h Simplify some more. 2009-07-17 21:06:58 +00:00
SjLjEHPrepare.cpp Check for shared landing pads when assigning call site values. Invokes which 2009-08-20 01:03:48 +00:00
Spiller.cpp Convert DOUT to DEBUG(errs()...). 2009-08-22 20:54:03 +00:00
Spiller.h Fix some minor MSVC compiler warnings. 2009-07-19 01:38:38 +00:00
StackProtector.cpp Push LLVMContexts through the IntegerType APIs. 2009-08-13 21:58:54 +00:00
StackSlotColoring.cpp Use setPreservesAll and setPreservesCFG in CodeGen passes. 2009-07-31 23:37:33 +00:00
StrongPHIElimination.cpp Modified VNInfo. The "copy" member is now a union which holds the copy for a register interval, or the defining register for a stack interval. Access is via getCopy/setCopy and getReg/setReg. 2009-08-10 23:43:28 +00:00
TargetInstrInfoImpl.cpp Let each target determines whether a machine instruction is dead. If true, that allows late codeine passes to delete it. 2009-07-22 00:25:27 +00:00
TwoAddressInstructionPass.cpp remove some DOUTs 2009-08-23 03:20:44 +00:00
UnreachableBlockElim.cpp Make UnreachableMachineBlockElim preserve MachineDominatorTree and 2009-08-01 00:34:30 +00:00
VirtRegMap.cpp Move more to raw_ostream, provide support for writing MachineBasicBlock, 2009-07-24 10:36:58 +00:00
VirtRegMap.h Move more to raw_ostream, provide support for writing MachineBasicBlock, 2009-07-24 10:36:58 +00:00
VirtRegRewriter.cpp remove some DOUTs 2009-08-23 03:20:44 +00:00
VirtRegRewriter.h Fixed a bug in LiveInterval scaling (failure to scale VNI defs correctly), removed old TODO comments. 2009-06-24 02:17:32 +00:00

README.txt

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvments:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4