forked from OSchip/llvm-project
199 lines
6.8 KiB
C++
199 lines
6.8 KiB
C++
//===-- RegUsageInfoCollector.cpp - Register Usage Information Collector --===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// This pass is required to take advantage of the interprocedural register
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/// allocation infrastructure.
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///
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/// This pass is simple MachineFunction pass which collects register usage
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/// details by iterating through each physical registers and checking
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/// MRI::isPhysRegUsed() then creates a RegMask based on this details.
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/// The pass then stores this RegMask in PhysicalRegisterUsageInfo.cpp
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegisterUsageInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "ip-regalloc"
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STATISTIC(NumCSROpt,
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"Number of functions optimized for callee saved registers");
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namespace llvm {
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void initializeRegUsageInfoCollectorPass(PassRegistry &);
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}
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namespace {
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class RegUsageInfoCollector : public MachineFunctionPass {
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public:
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RegUsageInfoCollector() : MachineFunctionPass(ID) {
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PassRegistry &Registry = *PassRegistry::getPassRegistry();
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initializeRegUsageInfoCollectorPass(Registry);
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}
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StringRef getPassName() const override {
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return "Register Usage Information Collector Pass";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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bool runOnMachineFunction(MachineFunction &MF) override;
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// Call determineCalleeSaves and then also set the bits for subregs and
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// fully saved superregs.
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static void computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF);
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static char ID;
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};
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} // end of anonymous namespace
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char RegUsageInfoCollector::ID = 0;
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INITIALIZE_PASS_BEGIN(RegUsageInfoCollector, "RegUsageInfoCollector",
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"Register Usage Information Collector", false, false)
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INITIALIZE_PASS_DEPENDENCY(PhysicalRegisterUsageInfo)
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INITIALIZE_PASS_END(RegUsageInfoCollector, "RegUsageInfoCollector",
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"Register Usage Information Collector", false, false)
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FunctionPass *llvm::createRegUsageInfoCollector() {
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return new RegUsageInfoCollector();
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}
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void RegUsageInfoCollector::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<PhysicalRegisterUsageInfo>();
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) {
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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const TargetMachine &TM = MF.getTarget();
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LLVM_DEBUG(dbgs() << " -------------------- " << getPassName()
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<< " -------------------- \n");
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LLVM_DEBUG(dbgs() << "Function Name : " << MF.getName() << "\n");
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std::vector<uint32_t> RegMask;
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// Compute the size of the bit vector to represent all the registers.
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// The bit vector is broken into 32-bit chunks, thus takes the ceil of
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// the number of registers divided by 32 for the size.
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unsigned RegMaskSize = MachineOperand::getRegMaskSize(TRI->getNumRegs());
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RegMask.resize(RegMaskSize, 0xFFFFFFFF);
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const Function &F = MF.getFunction();
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PhysicalRegisterUsageInfo *PRUI = &getAnalysis<PhysicalRegisterUsageInfo>();
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PRUI->setTargetMachine(&TM);
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LLVM_DEBUG(dbgs() << "Clobbered Registers: ");
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BitVector SavedRegs;
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computeCalleeSavedRegs(SavedRegs, MF);
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const BitVector &UsedPhysRegsMask = MRI->getUsedPhysRegsMask();
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auto SetRegAsDefined = [&RegMask] (unsigned Reg) {
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RegMask[Reg / 32] &= ~(1u << Reg % 32);
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};
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// Scan all the physical registers. When a register is defined in the current
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// function set it and all the aliasing registers as defined in the regmask.
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for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
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// Don't count registers that are saved and restored.
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if (SavedRegs.test(PReg))
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continue;
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// If a register is defined by an instruction mark it as defined together
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// with all it's unsaved aliases.
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if (!MRI->def_empty(PReg)) {
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for (MCRegAliasIterator AI(PReg, TRI, true); AI.isValid(); ++AI)
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if (!SavedRegs.test(*AI))
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SetRegAsDefined(*AI);
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continue;
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}
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// If a register is in the UsedPhysRegsMask set then mark it as defined.
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// All clobbered aliases will also be in the set, so we can skip setting
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// as defined all the aliases here.
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if (UsedPhysRegsMask.test(PReg))
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SetRegAsDefined(PReg);
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}
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if (TargetFrameLowering::isSafeForNoCSROpt(F)) {
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++NumCSROpt;
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LLVM_DEBUG(dbgs() << MF.getName()
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<< " function optimized for not having CSR.\n");
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}
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for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg)
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if (MachineOperand::clobbersPhysReg(&(RegMask[0]), PReg))
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LLVM_DEBUG(dbgs() << printReg(PReg, TRI) << " ");
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LLVM_DEBUG(dbgs() << " \n----------------------------------------\n");
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PRUI->storeUpdateRegUsageInfo(&F, std::move(RegMask));
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return false;
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}
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void RegUsageInfoCollector::
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computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) {
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const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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// Target will return the set of registers that it saves/restores as needed.
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SavedRegs.clear();
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TFI->determineCalleeSaves(MF, SavedRegs);
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// Insert subregs.
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const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
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for (unsigned i = 0; CSRegs[i]; ++i) {
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unsigned Reg = CSRegs[i];
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if (SavedRegs.test(Reg))
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for (MCSubRegIterator SR(Reg, TRI, false); SR.isValid(); ++SR)
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SavedRegs.set(*SR);
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}
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// Insert any register fully saved via subregisters.
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for (unsigned PReg = 1, PRegE = TRI->getNumRegs(); PReg < PRegE; ++PReg) {
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if (SavedRegs.test(PReg))
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continue;
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// Check if PReg is fully covered by its subregs.
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bool CoveredBySubRegs = false;
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for (const TargetRegisterClass *RC : TRI->regclasses())
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if (RC->CoveredBySubRegs && RC->contains(PReg)) {
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CoveredBySubRegs = true;
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break;
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}
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if (!CoveredBySubRegs)
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continue;
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// Add PReg to SavedRegs if all subregs are saved.
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bool AllSubRegsSaved = true;
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for (MCSubRegIterator SR(PReg, TRI, false); SR.isValid(); ++SR)
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if (!SavedRegs.test(*SR)) {
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AllSubRegsSaved = false;
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break;
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}
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if (AllSubRegsSaved)
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SavedRegs.set(PReg);
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}
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}
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