forked from OSchip/llvm-project
131 lines
3.4 KiB
YAML
131 lines
3.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
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--- |
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define void @test_mul_i1() { ret void}
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define i16 @test_mul_i16(i16 %arg1, i16 %arg2) {
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%ret = mul i16 %arg1, %arg2
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ret i16 %ret
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}
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define i32 @test_mul_i32(i32 %arg1, i32 %arg2) {
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%ret = mul i32 %arg1, %arg2
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ret i32 %ret
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}
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define i64 @test_mul_i64(i64 %arg1, i64 %arg2) {
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%ret = mul i64 %arg1, %arg2
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ret i64 %ret
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}
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...
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---
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name: test_mul_i1
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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; CHECK-LABEL: name: test_mul_i1
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
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; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
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; CHECK: [[MUL:%[0-9]+]]:_(s8) = G_MUL [[TRUNC]], [[TRUNC1]]
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; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
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; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
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; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY [[MUL]](s8)
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; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY1]], [[C]]
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; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
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; CHECK: RET 0
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%0(s32) = COPY $edx
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%1(s1) = G_TRUNC %0(s32)
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%2(s1) = G_MUL %1, %1
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%3:_(p0) = G_IMPLICIT_DEF
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G_STORE %2, %3 :: (store 1)
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RET 0
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...
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---
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name: test_mul_i16
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_mul_i16
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; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
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; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY $si
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; CHECK: [[MUL:%[0-9]+]]:_(s16) = G_MUL [[COPY]], [[COPY1]]
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; CHECK: $ax = COPY [[MUL]](s16)
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; CHECK: RET 0, implicit $ax
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%0(s16) = COPY $di
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%1(s16) = COPY $si
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%2(s16) = G_MUL %0, %1
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$ax = COPY %2(s16)
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RET 0, implicit $ax
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...
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---
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name: test_mul_i32
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $edi, $esi
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; CHECK-LABEL: name: test_mul_i32
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
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; CHECK: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[COPY]], [[COPY1]]
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; CHECK: $eax = COPY [[MUL]](s32)
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; CHECK: RET 0, implicit $eax
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%0(s32) = COPY $edi
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%1(s32) = COPY $esi
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%2(s32) = G_MUL %0, %1
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$eax = COPY %2(s32)
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RET 0, implicit $eax
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...
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---
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name: test_mul_i64
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _ }
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- { id: 1, class: _ }
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- { id: 2, class: _ }
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi, $rsi
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; CHECK-LABEL: name: test_mul_i64
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; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
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; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
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; CHECK: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[COPY]], [[COPY1]]
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; CHECK: $rax = COPY [[MUL]](s64)
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; CHECK: RET 0, implicit $rax
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%0(s64) = COPY $rdi
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%1(s64) = COPY $rsi
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%2(s64) = G_MUL %0, %1
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$rax = COPY %2(s64)
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RET 0, implicit $rax
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...
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