forked from OSchip/llvm-project
113 lines
4.4 KiB
YAML
113 lines
4.4 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X64
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# RUN: llc -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=X32
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--- |
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define void @test_memop_s8tos32() {
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ret void
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}
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define void @test_memop_s64() {
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ret void
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}
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...
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---
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name: test_memop_s8tos32
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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- { id: 3, class: _, preferred-register: '' }
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- { id: 4, class: _, preferred-register: '' }
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- { id: 5, class: _, preferred-register: '' }
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- { id: 6, class: _, preferred-register: '' }
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- { id: 7, class: _, preferred-register: '' }
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- { id: 8, class: _, preferred-register: '' }
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- { id: 9, class: _, preferred-register: '' }
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- { id: 10, class: _, preferred-register: '' }
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi
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; X64-LABEL: name: test_memop_s8tos32
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; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
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; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
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; X64: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
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; X64: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load 2)
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; X64: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4)
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; X64: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 8)
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; X64: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
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; X64: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
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; X64: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]]
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; X64: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
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; X64: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1)
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; X64: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2)
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; X64: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store 4)
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; X64: G_STORE [[LOAD4]](p0), [[DEF]](p0) :: (store 8)
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; X32-LABEL: name: test_memop_s8tos32
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; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
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; X32: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
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; X32: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
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; X32: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load 2)
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; X32: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4)
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; X32: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load 8)
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; X32: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
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; X32: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
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; X32: [[AND:%[0-9]+]]:_(s8) = G_AND [[COPY]], [[C]]
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; X32: G_STORE [[AND]](s8), [[DEF]](p0) :: (store 1)
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; X32: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store 1)
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; X32: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store 2)
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; X32: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store 4)
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; X32: G_STORE [[LOAD4]](p0), [[DEF]](p0) :: (store 8)
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%0(p0) = IMPLICIT_DEF
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%9(s1) = G_LOAD %0(p0) :: (load 1)
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%1(s8) = G_LOAD %0(p0) :: (load 1)
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%2(s16) = G_LOAD %0(p0) :: (load 2)
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%3(s32) = G_LOAD %0(p0) :: (load 4)
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%4(p0) = G_LOAD %0(p0) :: (load 8)
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G_STORE %9, %0 :: (store 1)
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G_STORE %1, %0 :: (store 1)
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G_STORE %2, %0 :: (store 2)
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G_STORE %3, %0 :: (store 4)
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G_STORE %4, %0 :: (store 8)
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...
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---
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name: test_memop_s64
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alignment: 4
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legalized: false
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regBankSelected: false
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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- { id: 2, class: _, preferred-register: '' }
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liveins:
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#
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body: |
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bb.1 (%ir-block.0):
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liveins: $rdi
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; X64-LABEL: name: test_memop_s64
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; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
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; X64: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[DEF]](p0) :: (load 8)
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; X64: G_STORE [[LOAD]](s64), [[DEF]](p0) :: (store 8)
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; X32-LABEL: name: test_memop_s64
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; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
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; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4, align 8)
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; X32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; X32: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C]](s32)
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; X32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP]](p0) :: (load 4)
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; X32: G_STORE [[LOAD]](s32), [[DEF]](p0) :: (store 4, align 8)
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; X32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; X32: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[DEF]], [[C1]](s32)
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; X32: G_STORE [[LOAD1]](s32), [[GEP1]](p0) :: (store 4)
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%0(p0) = IMPLICIT_DEF
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%1(s64) = G_LOAD %0(p0) :: (load 8)
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G_STORE %1, %0 :: (store 8)
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...
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