forked from OSchip/llvm-project
584 lines
21 KiB
YAML
584 lines
21 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: test_min_max_ValK0_K1_f32
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: true
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_min_max_ValK0_K1_f32
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_CLAMP [[FMUL]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)
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%0:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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%9:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_FMUL %0, %9
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%4:sgpr(s32) = G_FCONSTANT float 0.000000e+00
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%10:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = nnan G_FMAXNUM_IEEE %3, %10
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%6:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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%11:vgpr(s32) = COPY %6(s32)
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%7:vgpr(s32) = nnan G_FMINNUM_IEEE %5, %11
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$vgpr0 = COPY %7(s32)
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...
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---
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name: test_min_max_K0Val_K1_f64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: false
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_min_max_K0Val_K1_f64
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 2.000000e+00
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s64) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s64) = nnan G_AMDGPU_CLAMP [[FMUL]]
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AMDGPU_CLAMP]](s64)
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%4:sgpr(s64) = G_FCONSTANT double 2.000000e+00
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%13:vgpr(s64) = COPY %4(s64)
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%5:vgpr(s64) = G_FMUL %0, %13
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%6:sgpr(s64) = G_FCONSTANT double 0.000000e+00
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%14:vgpr(s64) = COPY %6(s64)
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%7:vgpr(s64) = nnan G_FMAXNUM %14, %5
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%8:sgpr(s64) = G_FCONSTANT double 1.000000e+00
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%15:vgpr(s64) = COPY %8(s64)
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%9:vgpr(s64) = nnan G_FMINNUM %7, %15
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$vgpr0_vgpr1 = COPY %9(s64)
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...
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---
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name: test_min_K1max_ValK0_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: true
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_min_K1max_ValK0_f16
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]]
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; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s16) = G_FCANONICALIZE [[FMUL]]
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; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = G_AMDGPU_CLAMP [[FCANONICALIZE]]
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_CLAMP]](s16)
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; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
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%2:vgpr(s32) = COPY $vgpr0
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%0:vgpr(s16) = G_TRUNC %2(s32)
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%3:sgpr(s16) = G_FCONSTANT half 0xH4000
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%12:vgpr(s16) = COPY %3(s16)
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%4:vgpr(s16) = G_FMUL %0, %12
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%5:sgpr(s16) = G_FCONSTANT half 0xH0000
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%11:vgpr(s16) = G_FCANONICALIZE %4
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%13:vgpr(s16) = COPY %5(s16)
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%6:vgpr(s16) = G_FMAXNUM_IEEE %11, %13
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%7:sgpr(s16) = G_FCONSTANT half 0xH3C00
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%14:vgpr(s16) = COPY %7(s16)
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%8:vgpr(s16) = G_FMINNUM_IEEE %14, %6
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%10:vgpr(s32) = G_ANYEXT %8(s16)
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$vgpr0 = COPY %10(s32)
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...
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---
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name: test_min_K1max_K0Val_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: false
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_min_K1max_K0Val_f16
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16)
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; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32)
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(<2 x s16>) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(<2 x s16>) = nnan G_AMDGPU_CLAMP [[FMUL]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](<2 x s16>)
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%3:sgpr(s16) = G_FCONSTANT half 0xH4000
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%12:sgpr(s32) = G_ANYEXT %3(s16)
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%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %12(s32), %12(s32)
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%6:sgpr(s16) = G_FCONSTANT half 0xH0000
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%13:sgpr(s32) = G_ANYEXT %6(s16)
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%5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %13(s32), %13(s32)
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%9:sgpr(s16) = G_FCONSTANT half 0xH3C00
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%14:sgpr(s32) = G_ANYEXT %9(s16)
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%8:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %14(s32), %14(s32)
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%15:vgpr(<2 x s16>) = COPY %2(<2 x s16>)
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%4:vgpr(<2 x s16>) = G_FMUL %0, %15
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%16:vgpr(<2 x s16>) = COPY %5(<2 x s16>)
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%7:vgpr(<2 x s16>) = nnan G_FMAXNUM %16, %4
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%17:vgpr(<2 x s16>) = COPY %8(<2 x s16>)
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%10:vgpr(<2 x s16>) = nnan G_FMINNUM %17, %7
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$vgpr0 = COPY %10(<2 x s16>)
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...
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---
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name: test_min_max_splat_padded_with_undef
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: true
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_min_max_splat_padded_with_undef
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16)
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; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32)
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(<2 x s16>) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(<2 x s16>) = G_FCANONICALIZE [[FMUL]]
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; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(<2 x s16>) = G_AMDGPU_CLAMP [[FCANONICALIZE]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](<2 x s16>)
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%3:sgpr(s16) = G_FCONSTANT half 0xH4000
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%17:sgpr(s32) = G_ANYEXT %3(s16)
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%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %17(s32), %17(s32)
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%6:sgpr(s16) = G_FCONSTANT half 0xH0000
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%18:sgpr(s32) = G_ANYEXT %6(s16)
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%19:sgpr(s32) = G_IMPLICIT_DEF
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%5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %18(s32), %19(s32)
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%10:sgpr(s16) = G_FCONSTANT half 0xH3C00
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%20:sgpr(s32) = G_ANYEXT %10(s16)
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%9:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %20(s32), %19(s32)
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%21:vgpr(<2 x s16>) = COPY %2(<2 x s16>)
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%4:vgpr(<2 x s16>) = G_FMUL %0, %21
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%16:vgpr(<2 x s16>) = G_FCANONICALIZE %4
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%22:vgpr(<2 x s16>) = COPY %5(<2 x s16>)
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%8:vgpr(<2 x s16>) = G_FMAXNUM_IEEE %22, %16
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%23:vgpr(<2 x s16>) = COPY %9(<2 x s16>)
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%11:vgpr(<2 x s16>) = G_FMINNUM_IEEE %23, %8
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$vgpr0 = COPY %11(<2 x s16>)
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...
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---
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name: test_max_min_ValK1_K0_f32
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machineFunctionInfo:
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mode:
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ieee: true
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_max_min_ValK1_K0_f32
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s32) = nnan G_AMDGPU_CLAMP [[FMUL]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](s32)
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%0:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
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%9:vgpr(s32) = COPY %2(s32)
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%3:vgpr(s32) = G_FMUL %0, %9
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%4:sgpr(s32) = G_FCONSTANT float 1.000000e+00
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%10:vgpr(s32) = COPY %4(s32)
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%5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %10
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%6:sgpr(s32) = G_FCONSTANT float 0.000000e+00
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%11:vgpr(s32) = COPY %6(s32)
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%7:vgpr(s32) = nnan G_FMAXNUM_IEEE %5, %11
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$vgpr0 = COPY %7(s32)
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...
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---
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name: test_max_min_K1Val_K0_f64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: false
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: test_max_min_K1Val_K0_f64
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_FCONSTANT double 2.000000e+00
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY [[C]](s64)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s64) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s64) = nnan G_AMDGPU_CLAMP [[FMUL]]
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AMDGPU_CLAMP]](s64)
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%0:vgpr(s64) = COPY $vgpr0_vgpr1
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%4:sgpr(s64) = G_FCONSTANT double 2.000000e+00
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%13:vgpr(s64) = COPY %4(s64)
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%5:vgpr(s64) = G_FMUL %0, %13
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%6:sgpr(s64) = G_FCONSTANT double 1.000000e+00
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%14:vgpr(s64) = COPY %6(s64)
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%7:vgpr(s64) = nnan G_FMINNUM %14, %5
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%8:sgpr(s64) = G_FCONSTANT double 0.000000e+00
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%15:vgpr(s64) = COPY %8(s64)
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%9:vgpr(s64) = nnan G_FMAXNUM %7, %15
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$vgpr0_vgpr1 = COPY %9(s64)
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...
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---
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name: test_max_K0min_ValK1_f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: true
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_max_K0min_ValK1_f16
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s16) = COPY [[C]](s16)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s16) = G_FMUL [[TRUNC]], [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(s16) = nnan G_AMDGPU_CLAMP [[FMUL]]
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:vgpr(s32) = G_ANYEXT [[AMDGPU_CLAMP]](s16)
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; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32)
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%2:vgpr(s32) = COPY $vgpr0
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%0:vgpr(s16) = G_TRUNC %2(s32)
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%3:sgpr(s16) = G_FCONSTANT half 0xH4000
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%11:vgpr(s16) = COPY %3(s16)
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%4:vgpr(s16) = G_FMUL %0, %11
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%5:sgpr(s16) = G_FCONSTANT half 0xH3C00
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%12:vgpr(s16) = COPY %5(s16)
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%6:vgpr(s16) = nnan G_FMINNUM_IEEE %4, %12
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%7:sgpr(s16) = G_FCONSTANT half 0xH0000
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%13:vgpr(s16) = COPY %7(s16)
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%8:vgpr(s16) = nnan G_FMAXNUM_IEEE %13, %6
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%10:vgpr(s32) = G_ANYEXT %8(s16)
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$vgpr0 = COPY %10(s32)
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...
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---
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name: test_max_K0min_K1Val_v2f16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: false
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dx10-clamp: true
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body: |
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bb.1 :
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liveins: $vgpr0
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; CHECK-LABEL: name: test_max_K0min_K1Val_v2f16
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s16) = G_FCONSTANT half 0xH4000
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; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[C]](s16)
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; CHECK-NEXT: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[ANYEXT]](s32), [[ANYEXT]](s32)
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>)
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; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(<2 x s16>) = G_FMUL [[COPY]], [[COPY1]]
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; CHECK-NEXT: [[AMDGPU_CLAMP:%[0-9]+]]:vgpr(<2 x s16>) = nnan G_AMDGPU_CLAMP [[FMUL]]
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; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_CLAMP]](<2 x s16>)
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%0:vgpr(<2 x s16>) = COPY $vgpr0
|
|
%3:sgpr(s16) = G_FCONSTANT half 0xH4000
|
|
%13:sgpr(s32) = G_ANYEXT %3(s16)
|
|
%2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %13(s32), %13(s32)
|
|
%6:sgpr(s16) = G_FCONSTANT half 0xH3C00
|
|
%14:sgpr(s32) = G_ANYEXT %6(s16)
|
|
%15:sgpr(s32) = G_IMPLICIT_DEF
|
|
%5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %14(s32), %15(s32)
|
|
%10:sgpr(s16) = G_FCONSTANT half 0xH0000
|
|
%16:sgpr(s32) = G_ANYEXT %10(s16)
|
|
%9:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %15(s32), %16(s32)
|
|
%17:vgpr(<2 x s16>) = COPY %2(<2 x s16>)
|
|
%4:vgpr(<2 x s16>) = G_FMUL %0, %17
|
|
%18:vgpr(<2 x s16>) = COPY %5(<2 x s16>)
|
|
%8:vgpr(<2 x s16>) = nnan G_FMINNUM %18, %4
|
|
%19:vgpr(<2 x s16>) = COPY %9(<2 x s16>)
|
|
%11:vgpr(<2 x s16>) = nnan G_FMAXNUM %19, %8
|
|
$vgpr0 = COPY %11(<2 x s16>)
|
|
...
|
|
|
|
# FixMe: add tests with attributes #3 = {"no-nans-fp-math"="true"}
|
|
|
|
---
|
|
name: test_min_max_K0_gt_K1
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo:
|
|
mode:
|
|
ieee: true
|
|
dx10-clamp: true
|
|
body: |
|
|
bb.1 :
|
|
liveins: $vgpr0
|
|
|
|
; CHECK-LABEL: name: test_min_max_K0_gt_K1
|
|
; CHECK: liveins: $vgpr0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
|
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
|
|
; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
|
|
; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[FMAXNUM_IEEE]], [[COPY2]]
|
|
; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32)
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%2:sgpr(s32) = G_FCONSTANT float 1.000000e+00
|
|
%7:vgpr(s32) = COPY %2(s32)
|
|
%3:vgpr(s32) = nnan G_FMAXNUM_IEEE %0, %7
|
|
%4:sgpr(s32) = G_FCONSTANT float 0.000000e+00
|
|
%8:vgpr(s32) = COPY %4(s32)
|
|
%5:vgpr(s32) = nnan G_FMINNUM_IEEE %3, %8
|
|
$vgpr0 = COPY %5(s32)
|
|
...
|
|
|
|
---
|
|
name: test_max_min_K0_gt_K1
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo:
|
|
mode:
|
|
ieee: true
|
|
dx10-clamp: true
|
|
body: |
|
|
bb.1 :
|
|
liveins: $vgpr0
|
|
|
|
; CHECK-LABEL: name: test_max_min_K0_gt_K1
|
|
; CHECK: liveins: $vgpr0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
|
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
|
|
; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMINNUM_IEEE [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
|
|
; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = nnan G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY2]]
|
|
; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%2:sgpr(s32) = G_FCONSTANT float 0.000000e+00
|
|
%7:vgpr(s32) = COPY %2(s32)
|
|
%3:vgpr(s32) = nnan G_FMINNUM_IEEE %0, %7
|
|
%4:sgpr(s32) = G_FCONSTANT float 1.000000e+00
|
|
%8:vgpr(s32) = COPY %4(s32)
|
|
%5:vgpr(s32) = nnan G_FMAXNUM_IEEE %3, %8
|
|
$vgpr0 = COPY %5(s32)
|
|
...
|
|
|
|
---
|
|
name: test_min_max_maybe_NaN_input_ieee_false
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo:
|
|
mode:
|
|
ieee: false
|
|
dx10-clamp: true
|
|
body: |
|
|
bb.1 :
|
|
liveins: $vgpr0
|
|
|
|
; CHECK-LABEL: name: test_min_max_maybe_NaN_input_ieee_false
|
|
; CHECK: liveins: $vgpr0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
|
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
|
|
; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
|
|
; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMUL]], [[COPY2]]
|
|
; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)
|
|
; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMAXNUM]], [[COPY3]]
|
|
; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM]](s32)
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
|
|
%9:vgpr(s32) = COPY %2(s32)
|
|
%3:vgpr(s32) = G_FMUL %0, %9
|
|
%4:sgpr(s32) = G_FCONSTANT float 0.000000e+00
|
|
%10:vgpr(s32) = COPY %4(s32)
|
|
%5:vgpr(s32) = G_FMAXNUM %3, %10
|
|
%6:sgpr(s32) = G_FCONSTANT float 1.000000e+00
|
|
%11:vgpr(s32) = COPY %6(s32)
|
|
%7:vgpr(s32) = G_FMINNUM %5, %11
|
|
$vgpr0 = COPY %7(s32)
|
|
...
|
|
|
|
---
|
|
name: test_min_max_maybe_NaN_input_ieee_true_dx10clamp_false
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo:
|
|
mode:
|
|
ieee: true
|
|
dx10-clamp: false
|
|
body: |
|
|
bb.1 :
|
|
liveins: $vgpr0
|
|
|
|
; CHECK-LABEL: name: test_min_max_maybe_NaN_input_ieee_true_dx10clamp_false
|
|
; CHECK: liveins: $vgpr0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
|
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
|
|
; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00
|
|
; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[FMUL]]
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
|
|
; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)
|
|
; CHECK-NEXT: [[AMDGPU_FMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FMED3 [[FCANONICALIZE]], [[COPY2]], [[COPY3]]
|
|
; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMED3_]](s32)
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
|
|
%10:vgpr(s32) = COPY %2(s32)
|
|
%3:vgpr(s32) = G_FMUL %0, %10
|
|
%4:sgpr(s32) = G_FCONSTANT float 0.000000e+00
|
|
%9:vgpr(s32) = G_FCANONICALIZE %3
|
|
%11:vgpr(s32) = COPY %4(s32)
|
|
%5:vgpr(s32) = G_FMAXNUM_IEEE %9, %11
|
|
%6:sgpr(s32) = G_FCONSTANT float 1.000000e+00
|
|
%12:vgpr(s32) = COPY %6(s32)
|
|
%7:vgpr(s32) = G_FMINNUM_IEEE %5, %12
|
|
$vgpr0 = COPY %7(s32)
|
|
...
|
|
|
|
---
|
|
name: test_max_min_maybe_NaN_input_ieee_true
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo:
|
|
mode:
|
|
ieee: true
|
|
dx10-clamp: true
|
|
body: |
|
|
bb.1 :
|
|
liveins: $vgpr0
|
|
|
|
; CHECK-LABEL: name: test_max_min_maybe_NaN_input_ieee_true
|
|
; CHECK: liveins: $vgpr0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
|
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
|
|
; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
|
|
; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:vgpr(s32) = G_FCANONICALIZE [[FMUL]]
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
|
|
; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMINNUM_IEEE [[FCANONICALIZE]], [[COPY2]]
|
|
; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)
|
|
; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:vgpr(s32) = G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[COPY3]]
|
|
; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
|
|
%10:vgpr(s32) = COPY %2(s32)
|
|
%3:vgpr(s32) = G_FMUL %0, %10
|
|
%4:sgpr(s32) = G_FCONSTANT float 1.000000e+00
|
|
%9:vgpr(s32) = G_FCANONICALIZE %3
|
|
%11:vgpr(s32) = COPY %4(s32)
|
|
%5:vgpr(s32) = G_FMINNUM_IEEE %9, %11
|
|
%6:sgpr(s32) = G_FCONSTANT float 0.000000e+00
|
|
%12:vgpr(s32) = COPY %6(s32)
|
|
%7:vgpr(s32) = G_FMAXNUM_IEEE %5, %12
|
|
$vgpr0 = COPY %7(s32)
|
|
...
|
|
|
|
---
|
|
name: test_max_min_maybe_NaN_input_ieee_false
|
|
legalized: true
|
|
regBankSelected: true
|
|
tracksRegLiveness: true
|
|
machineFunctionInfo:
|
|
mode:
|
|
ieee: false
|
|
dx10-clamp: true
|
|
body: |
|
|
bb.1 :
|
|
liveins: $vgpr0
|
|
|
|
; CHECK-LABEL: name: test_max_min_maybe_NaN_input_ieee_false
|
|
; CHECK: liveins: $vgpr0
|
|
; CHECK-NEXT: {{ $}}
|
|
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
|
; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 2.000000e+00
|
|
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)
|
|
; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]
|
|
; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 1.000000e+00
|
|
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)
|
|
; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:vgpr(s32) = G_FMINNUM [[FMUL]], [[COPY2]]
|
|
; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00
|
|
; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C2]](s32)
|
|
; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:vgpr(s32) = G_FMAXNUM [[FMINNUM]], [[COPY3]]
|
|
; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32)
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%2:sgpr(s32) = G_FCONSTANT float 2.000000e+00
|
|
%9:vgpr(s32) = COPY %2(s32)
|
|
%3:vgpr(s32) = G_FMUL %0, %9
|
|
%4:sgpr(s32) = G_FCONSTANT float 1.000000e+00
|
|
%10:vgpr(s32) = COPY %4(s32)
|
|
%5:vgpr(s32) = G_FMINNUM %3, %10
|
|
%6:sgpr(s32) = G_FCONSTANT float 0.000000e+00
|
|
%11:vgpr(s32) = COPY %6(s32)
|
|
%7:vgpr(s32) = G_FMAXNUM %5, %11
|
|
$vgpr0 = COPY %7(s32)
|
|
...
|