forked from OSchip/llvm-project
721 lines
23 KiB
TableGen
721 lines
23 KiB
TableGen
//=- X86ScheduleBtVer2.td - X86 BtVer2 (Jaguar) Scheduling ---*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for AMD btver2 (Jaguar) to support
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// instruction scheduling and other instruction cost heuristics. Based off AMD Software
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// Optimization Guide for AMD Family 16h Processors & Instruction Latency appendix.
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//
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//===----------------------------------------------------------------------===//
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def BtVer2Model : SchedMachineModel {
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// All x86 instructions are modeled as a single micro-op, and btver2 can
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// decode 2 instructions per cycle.
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let IssueWidth = 2;
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let MicroOpBufferSize = 64; // Retire Control Unit
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let LoadLatency = 5; // FPU latency (worse case cf Integer 3 cycle latency)
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let HighLatency = 25;
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let MispredictPenalty = 14; // Minimum branch misdirection penalty
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let PostRAScheduler = 1;
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// FIXME: SSE4/AVX is unimplemented. This flag is set to allow
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// the scheduler to assign a default model to unrecognized opcodes.
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let CompleteModel = 0;
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}
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let SchedModel = BtVer2Model in {
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// Jaguar can issue up to 6 micro-ops in one cycle
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def JALU0 : ProcResource<1>; // Integer Pipe0: integer ALU0 (also handle FP->INT jam)
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def JALU1 : ProcResource<1>; // Integer Pipe1: integer ALU1/MUL/DIV
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def JLAGU : ProcResource<1>; // Integer Pipe2: LAGU
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def JSAGU : ProcResource<1>; // Integer Pipe3: SAGU (also handles 3-operand LEA)
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def JFPU0 : ProcResource<1>; // Vector/FPU Pipe0: VALU0/VIMUL/FPA
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def JFPU1 : ProcResource<1>; // Vector/FPU Pipe1: VALU1/STC/FPM
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// Any pipe - FIXME we need this until we can discriminate between int/fpu load/store/moves properly
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def JAny : ProcResGroup<[JALU0, JALU1, JLAGU, JSAGU, JFPU0, JFPU1]>;
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// Integer Pipe Scheduler
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def JALU01 : ProcResGroup<[JALU0, JALU1]> {
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let BufferSize=20;
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}
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// AGU Pipe Scheduler
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def JLSAGU : ProcResGroup<[JLAGU, JSAGU]> {
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let BufferSize=12;
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}
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// Fpu Pipe Scheduler
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def JFPU01 : ProcResGroup<[JFPU0, JFPU1]> {
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let BufferSize=18;
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}
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def JDiv : ProcResource<1>; // integer division
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def JMul : ProcResource<1>; // integer multiplication
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def JVALU0 : ProcResource<1>; // vector integer
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def JVALU1 : ProcResource<1>; // vector integer
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def JVIMUL : ProcResource<1>; // vector integer multiplication
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def JSTC : ProcResource<1>; // vector store/convert
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def JFPM : ProcResource<1>; // FP multiplication
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def JFPA : ProcResource<1>; // FP addition
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// Integer loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
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// cycles after the memory operand.
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def : ReadAdvance<ReadAfterLd, 3>;
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// Many SchedWrites are defined in pairs with and without a folded load.
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// Instructions with folded loads are usually micro-fused, so they only appear
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// as two micro-ops when dispatched by the schedulers.
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// This multiclass defines the resource usage for variants with and without
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// folded loads.
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multiclass JWriteResIntPair<X86FoldableSchedWrite SchedRW,
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ProcResourceKind ExePort,
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int Lat> {
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// Register variant is using a single cycle on ExePort.
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def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
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// Memory variant also uses a cycle on JLAGU and adds 3 cycles to the
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// latency.
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def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
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let Latency = !add(Lat, 3);
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}
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}
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multiclass JWriteResFpuPair<X86FoldableSchedWrite SchedRW,
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ProcResourceKind ExePort,
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int Lat> {
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// Register variant is using a single cycle on ExePort.
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def : WriteRes<SchedRW, [ExePort]> { let Latency = Lat; }
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// Memory variant also uses a cycle on JLAGU and adds 5 cycles to the
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// latency.
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def : WriteRes<SchedRW.Folded, [JLAGU, ExePort]> {
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let Latency = !add(Lat, 5);
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}
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}
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// A folded store needs a cycle on the SAGU for the store data.
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def : WriteRes<WriteRMW, [JSAGU]>;
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////////////////////////////////////////////////////////////////////////////////
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// Arithmetic.
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////////////////////////////////////////////////////////////////////////////////
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defm : JWriteResIntPair<WriteALU, JALU01, 1>;
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defm : JWriteResIntPair<WriteIMul, JALU1, 3>;
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def : WriteRes<WriteIMulH, [JALU1]> {
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let Latency = 6;
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let ResourceCycles = [4];
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}
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// FIXME 8/16 bit divisions
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def : WriteRes<WriteIDiv, [JALU1, JDiv]> {
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let Latency = 25;
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let ResourceCycles = [1, 25];
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}
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def : WriteRes<WriteIDivLd, [JALU1, JLAGU, JDiv]> {
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let Latency = 41;
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let ResourceCycles = [1, 1, 25];
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}
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// This is for simple LEAs with one or two input operands.
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// FIXME: SAGU 3-operand LEA
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def : WriteRes<WriteLEA, [JALU01]>;
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////////////////////////////////////////////////////////////////////////////////
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// Integer shifts and rotates.
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////////////////////////////////////////////////////////////////////////////////
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defm : JWriteResIntPair<WriteShift, JALU01, 1>;
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////////////////////////////////////////////////////////////////////////////////
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// Loads, stores, and moves, not folded with other operations.
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// FIXME: Split x86 and SSE load/store/moves
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteLoad, [JLAGU]> { let Latency = 5; }
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def : WriteRes<WriteStore, [JSAGU]>;
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def : WriteRes<WriteMove, [JAny]>;
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////////////////////////////////////////////////////////////////////////////////
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// Idioms that clear a register, like xorps %xmm0, %xmm0.
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// These can often bypass execution ports completely.
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteZero, []>;
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////////////////////////////////////////////////////////////////////////////////
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// Branches don't produce values, so they have no latency, but they still
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// consume resources. Indirect branches can fold loads.
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////////////////////////////////////////////////////////////////////////////////
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defm : JWriteResIntPair<WriteJump, JALU01, 1>;
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////////////////////////////////////////////////////////////////////////////////
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// Floating point. This covers both scalar and vector operations.
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// FIXME: should we bother splitting JFPU pipe + unit stages for fast instructions?
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// FIXME: Double precision latencies
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// FIXME: SS vs PS latencies
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// FIXME: ymm latencies
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////////////////////////////////////////////////////////////////////////////////
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defm : JWriteResFpuPair<WriteFAdd, JFPU0, 3>;
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defm : JWriteResFpuPair<WriteFMul, JFPU1, 2>;
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defm : JWriteResFpuPair<WriteFRcp, JFPU1, 2>;
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defm : JWriteResFpuPair<WriteFRsqrt, JFPU1, 2>;
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defm : JWriteResFpuPair<WriteFShuffle, JFPU01, 1>;
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defm : JWriteResFpuPair<WriteFBlend, JFPU01, 1>;
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defm : JWriteResFpuPair<WriteFShuffle256, JFPU01, 1>;
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def : WriteRes<WriteFSqrt, [JFPU1, JLAGU, JFPM]> {
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let Latency = 21;
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let ResourceCycles = [1, 1, 21];
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}
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def : WriteRes<WriteFSqrtLd, [JFPU1, JLAGU, JFPM]> {
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let Latency = 26;
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let ResourceCycles = [1, 1, 21];
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}
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def : WriteRes<WriteFDiv, [JFPU1, JLAGU, JFPM]> {
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let Latency = 19;
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let ResourceCycles = [1, 1, 19];
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}
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def : WriteRes<WriteFDivLd, [JFPU1, JLAGU, JFPM]> {
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let Latency = 24;
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let ResourceCycles = [1, 1, 19];
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}
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// FIXME: integer pipes
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defm : JWriteResFpuPair<WriteCvtF2I, JFPU1, 3>; // Float -> Integer.
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defm : JWriteResFpuPair<WriteCvtI2F, JFPU1, 3>; // Integer -> Float.
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defm : JWriteResFpuPair<WriteCvtF2F, JFPU1, 3>; // Float -> Float size conversion.
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def : WriteRes<WriteFVarBlend, [JFPU01]> {
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let Latency = 2;
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let ResourceCycles = [4];
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let NumMicroOps = 3;
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}
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def : WriteRes<WriteFVarBlendLd, [JLAGU, JFPU01]> {
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let Latency = 7;
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let ResourceCycles = [1, 4];
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let NumMicroOps = 3;
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}
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// Vector integer operations.
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defm : JWriteResFpuPair<WriteVecALU, JFPU01, 1>;
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defm : JWriteResFpuPair<WriteVecShift, JFPU01, 1>;
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defm : JWriteResFpuPair<WriteVecIMul, JFPU0, 2>;
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defm : JWriteResFpuPair<WriteShuffle, JFPU01, 1>;
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defm : JWriteResFpuPair<WriteBlend, JFPU01, 1>;
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defm : JWriteResFpuPair<WriteVecLogic, JFPU01, 1>;
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defm : JWriteResFpuPair<WriteShuffle256, JFPU01, 1>;
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def : WriteRes<WriteVarBlend, [JFPU01]> {
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let Latency = 2;
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let ResourceCycles = [4];
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let NumMicroOps = 3;
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}
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def : WriteRes<WriteVarBlendLd, [JLAGU, JFPU01]> {
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let Latency = 7;
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let ResourceCycles = [1, 4];
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let NumMicroOps = 3;
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}
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// FIXME: why do we need to define AVX2 resource on CPU that doesn't have AVX2?
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def : WriteRes<WriteVarVecShift, [JFPU01]> {}
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def : WriteRes<WriteVarVecShiftLd, [JLAGU, JFPU01]> {
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let Latency = 6;
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let ResourceCycles = [1, 2];
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}
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def : WriteRes<WriteMPSAD, [JFPU0]> {
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let Latency = 3;
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let ResourceCycles = [2];
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}
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def : WriteRes<WriteMPSADLd, [JLAGU, JFPU0]> {
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let Latency = 8;
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let ResourceCycles = [1, 2];
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}
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////////////////////////////////////////////////////////////////////////////////
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// String instructions.
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// Packed Compare Implicit Length Strings, Return Mask
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// FIXME: approximate latencies + pipe dependencies
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WritePCmpIStrM, [JFPU01]> {
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let Latency = 7;
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let ResourceCycles = [2];
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}
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def : WriteRes<WritePCmpIStrMLd, [JLAGU, JFPU01]> {
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let Latency = 12;
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let ResourceCycles = [1, 2];
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}
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// Packed Compare Explicit Length Strings, Return Mask
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def : WriteRes<WritePCmpEStrM, [JFPU01]> {
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let Latency = 13;
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let ResourceCycles = [5];
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}
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def : WriteRes<WritePCmpEStrMLd, [JLAGU, JFPU01]> {
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let Latency = 18;
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let ResourceCycles = [1, 5];
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}
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// Packed Compare Implicit Length Strings, Return Index
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def : WriteRes<WritePCmpIStrI, [JFPU01]> {
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let Latency = 6;
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let ResourceCycles = [2];
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}
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def : WriteRes<WritePCmpIStrILd, [JLAGU, JFPU01]> {
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let Latency = 11;
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let ResourceCycles = [1, 2];
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}
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// Packed Compare Explicit Length Strings, Return Index
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def : WriteRes<WritePCmpEStrI, [JFPU01]> {
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let Latency = 13;
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let ResourceCycles = [5];
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}
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def : WriteRes<WritePCmpEStrILd, [JLAGU, JFPU01]> {
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let Latency = 18;
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let ResourceCycles = [1, 5];
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}
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////////////////////////////////////////////////////////////////////////////////
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// AES Instructions.
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteAESDecEnc, [JFPU01, JVIMUL]> {
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let Latency = 3;
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let ResourceCycles = [1, 1];
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}
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def : WriteRes<WriteAESDecEncLd, [JFPU01, JLAGU, JVIMUL]> {
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let Latency = 8;
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let ResourceCycles = [1, 1, 1];
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}
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def : WriteRes<WriteAESIMC, [JVIMUL]> {
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let Latency = 2;
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let ResourceCycles = [1];
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}
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def : WriteRes<WriteAESIMCLd, [JLAGU, JVIMUL]> {
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let Latency = 7;
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let ResourceCycles = [1, 1];
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}
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def : WriteRes<WriteAESKeyGen, [JVIMUL]> {
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let Latency = 2;
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let ResourceCycles = [1];
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}
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def : WriteRes<WriteAESKeyGenLd, [JLAGU, JVIMUL]> {
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let Latency = 7;
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let ResourceCycles = [1, 1];
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}
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////////////////////////////////////////////////////////////////////////////////
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// Horizontal add/sub instructions.
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteFHAdd, [JFPU0]> {
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let Latency = 3;
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}
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def : WriteRes<WriteFHAddLd, [JLAGU, JFPU0]> {
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let Latency = 8;
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}
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def : WriteRes<WritePHAdd, [JFPU01]> {
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let ResourceCycles = [1];
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}
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def : WriteRes<WritePHAddLd, [JLAGU, JFPU01 ]> {
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let Latency = 6;
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let ResourceCycles = [1, 1];
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}
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def WriteFHAddY: SchedWriteRes<[JFPU0]> {
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let Latency = 3;
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let ResourceCycles = [2];
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}
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def : InstRW<[WriteFHAddY], (instregex "VH(ADD|SUB)P(S|D)Yrr")>;
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def WriteFHAddYLd: SchedWriteRes<[JLAGU, JFPU0]> {
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let Latency = 8;
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let ResourceCycles = [1, 2];
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}
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def : InstRW<[WriteFHAddYLd], (instregex "VH(ADD|SUB)P(S|D)Yrm")>;
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////////////////////////////////////////////////////////////////////////////////
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// Carry-less multiplication instructions.
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////////////////////////////////////////////////////////////////////////////////
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def : WriteRes<WriteCLMul, [JVIMUL]> {
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let Latency = 2;
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let ResourceCycles = [1];
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}
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def : WriteRes<WriteCLMulLd, [JLAGU, JVIMUL]> {
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let Latency = 7;
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let ResourceCycles = [1, 1];
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}
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// FIXME: pipe for system/microcode?
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def : WriteRes<WriteSystem, [JAny]> { let Latency = 100; }
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def : WriteRes<WriteMicrocoded, [JAny]> { let Latency = 100; }
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def : WriteRes<WriteFence, [JSAGU]>;
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def : WriteRes<WriteNop, []>;
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////////////////////////////////////////////////////////////////////////////////
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// SSE4.1 instructions.
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////////////////////////////////////////////////////////////////////////////////
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def WriteDPPS: SchedWriteRes<[JFPU0, JFPU1]> {
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let Latency = 11;
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let ResourceCycles = [3,3];
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let NumMicroOps = 5;
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}
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def : InstRW<[WriteDPPS], (instregex "(V)?DPPSrri")>;
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def WriteDPPSLd: SchedWriteRes<[JLAGU, JFPU0, JFPU1]> {
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let Latency = 16;
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let ResourceCycles = [1,3,3];
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let NumMicroOps = 6;
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}
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def : InstRW<[WriteDPPSLd], (instregex "(V)?DPPSrmi")>;
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def WriteDPPD: SchedWriteRes<[JFPU0, JFPU1]> {
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let Latency = 9;
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let ResourceCycles = [3,3];
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let NumMicroOps = 3;
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}
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def : InstRW<[WriteDPPD], (instregex "(V)?DPPDrri")>;
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def WriteDPPDLd: SchedWriteRes<[JLAGU, JFPU0, JFPU1]> {
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let Latency = 14;
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let ResourceCycles = [1,3,3];
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let NumMicroOps = 3;
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}
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def : InstRW<[WriteDPPDLd], (instregex "(V)?DPPDrmi")>;
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////////////////////////////////////////////////////////////////////////////////
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// SSE4A instructions.
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////////////////////////////////////////////////////////////////////////////////
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def WriteEXTRQ: SchedWriteRes<[JFPU01]> {
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let Latency = 1;
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let ResourceCycles = [1];
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}
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def : InstRW<[WriteEXTRQ], (instregex "EXTRQ")>;
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def WriteINSERTQ: SchedWriteRes<[JFPU01]> {
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let Latency = 2;
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let ResourceCycles = [4];
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}
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def : InstRW<[WriteINSERTQ], (instregex "INSERTQ")>;
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////////////////////////////////////////////////////////////////////////////////
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// F16C instructions.
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////////////////////////////////////////////////////////////////////////////////
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def WriteCVT3: SchedWriteRes<[JFPU1]> {
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let Latency = 3;
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}
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def : InstRW<[WriteCVT3], (instregex "VCVTPS2PHrr")>;
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def : InstRW<[WriteCVT3], (instregex "VCVTPH2PSrr")>;
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def WriteCVT3St: SchedWriteRes<[JFPU1, JSAGU]> {
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let Latency = 3;
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let ResourceCycles = [1, 1];
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}
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def : InstRW<[WriteCVT3St], (instregex "VCVTPS2PHmr")>;
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def WriteCVT3Ld: SchedWriteRes<[JLAGU, JFPU1]> {
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let Latency = 8;
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let ResourceCycles = [1, 1];
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}
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def : InstRW<[WriteCVT3Ld], (instregex "VCVTPH2PSrm")>;
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def WriteCVTPS2PHY: SchedWriteRes<[JFPU1, JFPU01]> {
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let Latency = 6;
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let ResourceCycles = [2,2];
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let NumMicroOps = 3;
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}
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def : InstRW<[WriteCVTPS2PHY], (instregex "VCVTPS2PHYrr")>;
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def WriteCVTPS2PHYSt: SchedWriteRes<[JFPU1, JFPU01, JSAGU]> {
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let Latency = 11;
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let ResourceCycles = [2,2,1];
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let NumMicroOps = 3;
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}
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def : InstRW<[WriteCVTPS2PHYSt], (instregex "VCVTPS2PHYmr")>;
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def WriteCVTPH2PSY: SchedWriteRes<[JFPU1]> {
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let Latency = 3;
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let ResourceCycles = [2];
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let NumMicroOps = 2;
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}
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def : InstRW<[WriteCVTPH2PSY], (instregex "VCVTPH2PSYrr")>;
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def WriteCVTPH2PSYLd: SchedWriteRes<[JLAGU, JFPU1]> {
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let Latency = 8;
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let ResourceCycles = [1,2];
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let NumMicroOps = 2;
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}
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def : InstRW<[WriteCVTPH2PSYLd], (instregex "VCVTPH2PSYrm")>;
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////////////////////////////////////////////////////////////////////////////////
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// AVX instructions.
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////////////////////////////////////////////////////////////////////////////////
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def WriteVDPPSY: SchedWriteRes<[JFPU1, JFPU0]> {
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|
let Latency = 12;
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|
let ResourceCycles = [6, 6];
|
|
let NumMicroOps = 10;
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|
}
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|
def : InstRW<[WriteVDPPSY], (instregex "VDPPSYrr")>;
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|
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def WriteVDPPSYLd: SchedWriteRes<[JLAGU, JFPU1, JFPU0]> {
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|
let Latency = 17;
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|
let ResourceCycles = [1, 6, 6];
|
|
let NumMicroOps = 11;
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|
}
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|
def : InstRW<[WriteVDPPSYLd, ReadAfterLd], (instregex "VDPPSYrm")>;
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|
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def WriteFAddY: SchedWriteRes<[JFPU0]> {
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|
let Latency = 3;
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|
let ResourceCycles = [2];
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|
}
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|
def : InstRW<[WriteFAddY], (instregex "VADD(SUB)?P(S|D)Yrr", "VSUBP(S|D)Yrr")>;
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|
|
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def WriteFAddYLd: SchedWriteRes<[JLAGU, JFPU0]> {
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|
let Latency = 8;
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|
let ResourceCycles = [1, 2];
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|
}
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|
def : InstRW<[WriteFAddYLd, ReadAfterLd], (instregex "VADD(SUB)?P(S|D)Yrm", "VSUBP(S|D)Yrm")>;
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|
|
|
def WriteFDivY: SchedWriteRes<[JFPU1]> {
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|
let Latency = 38;
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|
let ResourceCycles = [38];
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|
}
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|
def : InstRW<[WriteFDivY], (instregex "VDIVP(D|S)Yrr")>;
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|
|
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def WriteFDivYLd: SchedWriteRes<[JLAGU, JFPU1]> {
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|
let Latency = 43;
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|
let ResourceCycles = [1, 38];
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|
}
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|
def : InstRW<[WriteFDivYLd, ReadAfterLd], (instregex "VDIVP(S|D)Yrm")>;
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|
|
|
def WriteVMULYPD: SchedWriteRes<[JFPU1]> {
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|
let Latency = 4;
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|
let ResourceCycles = [4];
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|
}
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|
def : InstRW<[WriteVMULYPD], (instregex "VMULPDYrr")>;
|
|
|
|
def WriteVMULYPDLd: SchedWriteRes<[JLAGU, JFPU1]> {
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|
let Latency = 9;
|
|
let ResourceCycles = [1, 4];
|
|
}
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|
def : InstRW<[WriteVMULYPDLd, ReadAfterLd], (instregex "VMULPDYrm")>;
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|
|
|
def WriteVMULYPS: SchedWriteRes<[JFPU1]> {
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|
let Latency = 2;
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|
let ResourceCycles = [2];
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|
}
|
|
def : InstRW<[WriteVMULYPS], (instregex "VMULPSYrr", "VRCPPSYr", "VRSQRTPSYr")>;
|
|
|
|
def WriteVMULYPSLd: SchedWriteRes<[JLAGU, JFPU1]> {
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|
let Latency = 7;
|
|
let ResourceCycles = [1, 2];
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|
}
|
|
def : InstRW<[WriteVMULYPSLd, ReadAfterLd], (instregex "VMULPSYrm", "VRCPPSYm", "VRSQRTPSYm")>;
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|
|
|
def WriteVCVTY: SchedWriteRes<[JSTC]> {
|
|
let Latency = 3;
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|
let ResourceCycles = [2];
|
|
}
|
|
def : InstRW<[WriteVCVTY], (instregex "VCVTDQ2P(S|D)Yrr")>;
|
|
def : InstRW<[WriteVCVTY], (instregex "VROUNDYP(S|D)r")>;
|
|
def : InstRW<[WriteVCVTY], (instregex "VCVTPS2DQYrr")>;
|
|
def : InstRW<[WriteVCVTY], (instregex "VCVTTPS2DQYrr")>;
|
|
|
|
def WriteVCVTYLd: SchedWriteRes<[JLAGU, JSTC]> {
|
|
let Latency = 8;
|
|
let ResourceCycles = [1, 2];
|
|
}
|
|
def : InstRW<[WriteVCVTYLd, ReadAfterLd], (instregex "VCVTDQ2P(S|D)Yrm")>;
|
|
def : InstRW<[WriteVCVTYLd, ReadAfterLd], (instregex "VROUNDYP(S|D)m")>;
|
|
def : InstRW<[WriteVCVTYLd, ReadAfterLd], (instregex "VCVTPS2DQYrm")>;
|
|
def : InstRW<[WriteVCVTYLd, ReadAfterLd], (instregex "VCVTTPS2DQYrm")>;
|
|
|
|
def WriteVMONTPSt: SchedWriteRes<[JSTC, JLAGU]> {
|
|
let Latency = 3;
|
|
let ResourceCycles = [2,1];
|
|
}
|
|
def : InstRW<[WriteVMONTPSt], (instregex "VMOVNTP(S|D)Ymr")>;
|
|
def : InstRW<[WriteVMONTPSt], (instregex "VMOVNTDQYmr")>;
|
|
|
|
def WriteVCVTPDY: SchedWriteRes<[JSTC, JFPU01]> {
|
|
let Latency = 6;
|
|
let ResourceCycles = [2, 4];
|
|
}
|
|
def : InstRW<[WriteVCVTPDY], (instregex "VCVTPD2(DQ|PS)Yrr")>;
|
|
def : InstRW<[WriteVCVTPDY], (instregex "VCVTTPD2DQYrr")>;
|
|
|
|
def WriteVCVTPDYLd: SchedWriteRes<[JLAGU, JSTC, JFPU01]> {
|
|
let Latency = 11;
|
|
let ResourceCycles = [1, 2, 4];
|
|
}
|
|
def : InstRW<[WriteVCVTPDYLd, ReadAfterLd], (instregex "VCVTPD2(DQ|PS)Yrm")>;
|
|
def : InstRW<[WriteVCVTPDYLd, ReadAfterLd], (instregex "VCVTTPD2DQYrm")>;
|
|
|
|
def WriteVBlendVPY: SchedWriteRes<[JFPU01]> {
|
|
let Latency = 3;
|
|
let ResourceCycles = [6];
|
|
}
|
|
def : InstRW<[WriteVBlendVPY], (instregex "VBLENDVP(S|D)Yrr", "VPERMILP(D|S)Yrr")>;
|
|
|
|
def WriteVBlendVPYLd: SchedWriteRes<[JLAGU, JFPU01]> {
|
|
let Latency = 8;
|
|
let ResourceCycles = [1, 6];
|
|
}
|
|
def : InstRW<[WriteVBlendVPYLd, ReadAfterLd], (instregex "VBLENDVP(S|D)Yrm")>;
|
|
|
|
def WriteVBROADCASTYLd: SchedWriteRes<[JLAGU, JFPU01]> {
|
|
let Latency = 6;
|
|
let ResourceCycles = [1, 4];
|
|
}
|
|
def : InstRW<[WriteVBROADCASTYLd, ReadAfterLd], (instregex "VBROADCASTS(S|D)Yrm")>;
|
|
|
|
def WriteFPAY22: SchedWriteRes<[JFPU0]> {
|
|
let Latency = 2;
|
|
let ResourceCycles = [2];
|
|
}
|
|
def : InstRW<[WriteFPAY22], (instregex "VCMPP(S|D)Yrri", "VM(AX|IN)P(D|S)Yrr")>;
|
|
|
|
def WriteFPAY22Ld: SchedWriteRes<[JLAGU, JFPU0]> {
|
|
let Latency = 7;
|
|
let ResourceCycles = [1, 2];
|
|
}
|
|
def : InstRW<[WriteFPAY22Ld, ReadAfterLd], (instregex "VCMPP(S|D)Yrmi", "VM(AX|IN)P(D|S)Yrm")>;
|
|
|
|
def WriteVHAddSubY: SchedWriteRes<[JFPU0]> {
|
|
let Latency = 3;
|
|
let ResourceCycles = [2];
|
|
}
|
|
def : InstRW<[WriteVHAddSubY], (instregex "VH(ADD|SUB)P(D|S)Yrr")>;
|
|
|
|
def WriteVHAddSubYLd: SchedWriteRes<[JLAGU, JFPU0]> {
|
|
let Latency = 8;
|
|
let ResourceCycles = [1, 2];
|
|
}
|
|
def : InstRW<[WriteVHAddSubYLd], (instregex "VH(ADD|SUB)P(D|S)Yrm")>;
|
|
|
|
def WriteVMaskMovLd: SchedWriteRes<[JLAGU,JFPU01]> {
|
|
let Latency = 6;
|
|
let ResourceCycles = [1, 2];
|
|
}
|
|
def : InstRW<[WriteVMaskMovLd], (instregex "VMASKMOVP(D|S)rm")>;
|
|
|
|
def WriteVMaskMovYLd: SchedWriteRes<[JLAGU,JFPU01]> {
|
|
let Latency = 6;
|
|
let ResourceCycles = [1, 4];
|
|
}
|
|
def : InstRW<[WriteVMaskMovYLd], (instregex "VMASKMOVP(D|S)Yrm")>;
|
|
|
|
def WriteVMaskMovSt: SchedWriteRes<[JFPU01,JSAGU]> {
|
|
let Latency = 6;
|
|
let ResourceCycles = [4, 1];
|
|
}
|
|
def : InstRW<[WriteVMaskMovSt], (instregex "VMASKMOVP(D|S)mr")>;
|
|
|
|
def WriteVMaskMovYSt: SchedWriteRes<[JFPU01,JSAGU]> {
|
|
let Latency = 6;
|
|
let ResourceCycles = [4, 1];
|
|
}
|
|
def : InstRW<[WriteVMaskMovYSt], (instregex "VMASKMOVP(D|S)Ymr")>;
|
|
|
|
// TODO: In fact we have latency '2+i'. The +i represents an additional 1 cycle transfer
|
|
// operation which moves the floating point result to the integer unit. During this
|
|
// additional cycle the floating point unit execution resources are not occupied
|
|
// and ALU0 in the integer unit is occupied instead.
|
|
def WriteVMOVMSK: SchedWriteRes<[JFPU0]> {
|
|
let Latency = 3;
|
|
}
|
|
def : InstRW<[WriteVMOVMSK], (instregex "VMOVMSKP(D|S)(Y)?rr")>;
|
|
|
|
// TODO: In fact we have latency '3+i'. The +i represents an additional 1 cycle transfer
|
|
// operation which moves the floating point result to the integer unit. During this
|
|
// additional cycle the floating point unit execution resources are not occupied
|
|
// and ALU0 in the integer unit is occupied instead.
|
|
def WriteVTESTY: SchedWriteRes<[JFPU01, JFPU0]> {
|
|
let Latency = 4;
|
|
let ResourceCycles = [2, 2];
|
|
let NumMicroOps = 3;
|
|
}
|
|
def : InstRW<[WriteVTESTY], (instregex "VTESTP(S|D)Yrr")>;
|
|
def : InstRW<[WriteVTESTY], (instregex "VPTESTYrr")>;
|
|
|
|
def WriteVTESTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPU0]> {
|
|
let Latency = 9;
|
|
let ResourceCycles = [1, 2, 2];
|
|
let NumMicroOps = 3;
|
|
}
|
|
def : InstRW<[WriteVTESTYLd], (instregex "VTESTP(S|D)Yrm")>;
|
|
def : InstRW<[WriteVTESTYLd], (instregex "VPTESTYrm")>;
|
|
|
|
def WriteVTEST: SchedWriteRes<[JFPU0]> {
|
|
let Latency = 3;
|
|
}
|
|
def : InstRW<[WriteVTEST], (instregex "VTESTP(S|D)rr")>;
|
|
def : InstRW<[WriteVTEST], (instregex "VPTESTrr")>;
|
|
|
|
def WriteVTESTLd: SchedWriteRes<[JLAGU, JFPU0]> {
|
|
let Latency = 8;
|
|
}
|
|
def : InstRW<[WriteVTESTLd], (instregex "VTESTP(S|D)rm")>;
|
|
def : InstRW<[WriteVTESTLd], (instregex "VPTESTrm")>;
|
|
|
|
def WriteVSQRTYPD: SchedWriteRes<[JFPU1]> {
|
|
let Latency = 54;
|
|
let ResourceCycles = [54];
|
|
}
|
|
def : InstRW<[WriteVSQRTYPD], (instregex "VSQRTPDYr")>;
|
|
|
|
def WriteVSQRTYPDLd: SchedWriteRes<[JLAGU, JFPU1]> {
|
|
let Latency = 59;
|
|
let ResourceCycles = [1, 54];
|
|
}
|
|
def : InstRW<[WriteVSQRTYPDLd], (instregex "VSQRTPDYm")>;
|
|
|
|
def WriteVSQRTYPS: SchedWriteRes<[JFPU1]> {
|
|
let Latency = 42;
|
|
let ResourceCycles = [42];
|
|
}
|
|
def : InstRW<[WriteVSQRTYPS], (instregex "VSQRTPSYr")>;
|
|
|
|
def WriteVSQRTYPSLd: SchedWriteRes<[JLAGU, JFPU1]> {
|
|
let Latency = 47;
|
|
let ResourceCycles = [1, 42];
|
|
}
|
|
def : InstRW<[WriteVSQRTYPSLd], (instregex "VSQRTPSYm")>;
|
|
|
|
def WriteJVZEROALL: SchedWriteRes<[]> {
|
|
let Latency = 90;
|
|
let NumMicroOps = 73;
|
|
}
|
|
def : InstRW<[WriteJVZEROALL], (instregex "VZEROALL")>;
|
|
|
|
def WriteJVZEROUPPER: SchedWriteRes<[]> {
|
|
let Latency = 46;
|
|
let NumMicroOps = 37;
|
|
}
|
|
def : InstRW<[WriteJVZEROUPPER], (instregex "VZEROUPPER")>;
|
|
} // SchedModel
|
|
|