forked from OSchip/llvm-project
64 lines
1.9 KiB
LLVM
64 lines
1.9 KiB
LLVM
; RUN: llc < %s -mtriple=arm64-eabi -mcpu=generic -aarch64-neon-syntax=apple | FileCheck %s
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define void @test0f(float* nocapture %x, float %a) #0 {
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entry:
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%0 = insertelement <4 x float> <float undef, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, float %a, i32 0
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%1 = bitcast float* %x to <4 x float>*
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store <4 x float> %0, <4 x float>* %1, align 16
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ret void
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; CHECK-LABEL: test0f
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; CHECK: movi.2d v[[TEMP:[0-9]+]], #0
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; CHECK: mov.s v[[TEMP]][0], v{{[0-9]+}}[0]
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; CHECK: str q[[TEMP]], [x0]
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; CHECK: ret
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}
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define void @test1f(float* nocapture %x, float %a) #0 {
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entry:
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%0 = insertelement <4 x float> <float undef, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, float %a, i32 0
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%1 = bitcast float* %x to <4 x float>*
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store <4 x float> %0, <4 x float>* %1, align 16
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ret void
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; CHECK-LABEL: test1f
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; CHECK: fmov.4s v[[TEMP:[0-9]+]], #1.0
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; CHECK: mov.s v[[TEMP]][0], v0[0]
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; CHECK: str q[[TEMP]], [x0]
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; CHECK: ret
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}
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; TODO: This should jsut be a dup + clearing lane 4.
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define <4 x float> @test2(float %a) {
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; CHECK-LABEL: test2:
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; CHECK: bb.0:
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; CHECK-NEXT: movi.2d v1, #0000000000000000
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; CHECK-NEXT: // kill
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; CHECK-NEXT: mov.s v1[0], v0[0]
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; CHECK-NEXT: mov.s v1[1], v0[0]
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; CHECK-NEXT: mov.s v1[2], v0[0]
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; CHECK-NEXT: mov.16b v0, v1
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; CHECK-NEXT: ret
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;
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entry:
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%0 = insertelement <4 x float> <float undef, float undef, float undef, float 0.000000e+00>, float %a, i32 0
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%1 = insertelement <4 x float> %0, float %a, i32 1
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%vecinit3 = insertelement <4 x float> %1, float %a, i32 2
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ret <4 x float> %vecinit3
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}
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; TODO: This should jsut be a mov.s v0[3], wzr
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define <4 x float> @test3(<4 x float> %a) #0 {
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; CHECK-LABEL: test3:
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; CHECK: bb.0:
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; CHECK-NEXT: fmov s1, wzr
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; CHECK-NEXT: mov.s v0[3], v1[0]
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; CHECK-NEXT: ret
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entry:
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%vecinit5 = insertelement <4 x float> %a, float 0.000000e+00, i32 3
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ret <4 x float> %vecinit5
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}
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