forked from OSchip/llvm-project
96 lines
2.5 KiB
C++
96 lines
2.5 KiB
C++
//===- AMDILRegisterInfo.h - AMDIL Register Information Impl ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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// This file contains the AMDIL implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef AMDILREGISTERINFO_H_
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#define AMDILREGISTERINFO_H_
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#include "llvm/Target/TargetRegisterInfo.h"
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#define GET_REGINFO_HEADER
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#include "AMDGPUGenRegisterInfo.inc"
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// See header file for explanation
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namespace llvm
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{
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class TargetInstrInfo;
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class Type;
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/// DWARFFlavour - Flavour of dwarf regnumbers
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///
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namespace DWARFFlavour {
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enum {
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AMDIL_Generic = 0
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};
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}
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struct AMDILRegisterInfo : public AMDILGenRegisterInfo
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{
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TargetMachine &TM;
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const TargetInstrInfo &TII;
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AMDILRegisterInfo(TargetMachine &tm, const TargetInstrInfo &tii);
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/// Code Generation virtual methods...
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const uint16_t * getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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const TargetRegisterClass* const*
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getCalleeSavedRegClasses(
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const MachineFunction *MF = 0) const;
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BitVector
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getReservedRegs(const MachineFunction &MF) const;
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BitVector
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getAllocatableSet(const MachineFunction &MF,
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const TargetRegisterClass *RC) const;
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void
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eliminateCallFramePseudoInstr(
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MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const;
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void
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eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, RegScavenger *RS = NULL) const;
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void
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processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
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// Debug information queries.
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unsigned int
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getRARegister() const;
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unsigned int
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getFrameRegister(const MachineFunction &MF) const;
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// Exception handling queries.
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unsigned int
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getEHExceptionRegister() const;
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unsigned int
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getEHHandlerRegister() const;
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int64_t
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getStackSize() const;
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virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT)
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const {
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return &AMDGPU::GPRI32RegClass;
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}
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private:
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mutable int64_t baseOffset;
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mutable int64_t nextFuncOffset;
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};
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} // end namespace llvm
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#endif // AMDILREGISTERINFO_H_
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