forked from OSchip/llvm-project
72 lines
2.9 KiB
Plaintext
72 lines
2.9 KiB
Plaintext
Date: Fri, 1 Jun 2001 17:08:44 -0500 (CDT)
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From: Chris Lattner <sabre@nondot.org>
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To: Vikram S. Adve <vadve@cs.uiuc.edu>
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Subject: RE: Interesting: GCC passes
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> That is very interesting. I agree that some of these could be done on LLVM
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> at link-time, but it is the extra time required that concerns me. Link-time
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> optimization is severely time-constrained.
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If we were to reimplement any of these optimizations, I assume that we
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could do them a translation unit at a time, just as GCC does now. This
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would lead to a pipeline like this:
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Static optimizations, xlation unit at a time:
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.c --GCC--> .llvm --llvmopt--> .llvm
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Link time optimizations:
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.llvm --llvm-ld--> .llvm --llvm-link-opt--> .llvm
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Of course, many optimizations could be shared between llvmopt and
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llvm-link-opt, but the wouldn't need to be shared... Thus compile time
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could be faster, because we are using a "smarter" IR (SSA based).
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> BTW, about SGI, "borrowing" SSA-based optimizations from one compiler and
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> putting it into another is not necessarily easier than re-doing it.
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> Optimization code is usually heavily tied in to the specific IR they use.
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Understood. The only reason that I brought this up is because SGI's IR is
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more similar to LLVM than it is different in many respects (SSA based,
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relatively low level, etc), and could be easily adapted. Also their
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optimizations are written in C++ and are actually somewhat
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structured... of course it would be no walk in the park, but it would be
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much less time consuming to adapt, say, SSA-PRE than to rewrite it.
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> But your larger point is valid that adding SSA based optimizations is
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> feasible and should be fun. (Again, link time cost is the issue.)
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Assuming linktime cost wasn't an issue, the question is:
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Does using GCC's backend buy us anything?
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> It also occurs to me that GCC is probably doing quite a bit of back-end
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> optimization (step 16 in your list). Do you have a breakdown of that?
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Not really. The irritating part of GCC is that it mixes it all up and
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doesn't have a clean separation of concerns. A lot of the "back end
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optimization" happens right along with other data optimizations (ie, CSE
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of machine specific things).
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As far as REAL back end optimizations go, it looks something like this:
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1. Instruction combination: try to make CISCy instructions, if available
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2. Register movement: try to get registers in the right places for the
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architecture to avoid register to register moves. For example, try to get
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the first argument of a function to naturally land in %o0 for sparc.
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3. Instruction scheduling: 'nuff said :)
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4. Register class preferencing: ??
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5. Local register allocation
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6. global register allocation
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7. Spilling
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8. Local regalloc
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9. Jump optimization
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10. Delay slot scheduling
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11. Branch shorting for CISC machines
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12. Instruction selection & peephole optimization
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13. Debug info output
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But none of this would be usable for LLVM anyways, unless we were using
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GCC as a static compiler.
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-Chris
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