forked from OSchip/llvm-project
176 lines
4.1 KiB
LLVM
176 lines
4.1 KiB
LLVM
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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define signext i8 @func1(i8 signext %a, i8 signext %b) {
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; CHECK-LABEL: func1:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
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; CHECK-NEXT: sla.w.sx %s0, %s0, 24
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; CHECK-NEXT: sra.w.sx %s0, %s0, 24
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul i8 %b, %a
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ret i8 %r
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}
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define signext i16 @func2(i16 signext %a, i16 signext %b) {
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; CHECK-LABEL: func2:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
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; CHECK-NEXT: sla.w.sx %s0, %s0, 16
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; CHECK-NEXT: sra.w.sx %s0, %s0, 16
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul i16 %b, %a
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ret i16 %r
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}
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define i32 @func3(i32 %a, i32 %b) {
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; CHECK-LABEL: func3:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul nsw i32 %b, %a
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ret i32 %r
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}
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define i64 @func4(i64 %a, i64 %b) {
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; CHECK-LABEL: func4:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.l %s0, %s1, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul nsw i64 %b, %a
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ret i64 %r
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}
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define zeroext i8 @func5(i8 zeroext %a, i8 zeroext %b) {
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; CHECK-LABEL: func5:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
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; CHECK-NEXT: and %s0, %s0, (56)0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul i8 %b, %a
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ret i8 %r
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}
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define zeroext i16 @func6(i16 zeroext %a, i16 zeroext %b) {
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; CHECK-LABEL: func6:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
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; CHECK-NEXT: and %s0, %s0, (48)0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul i16 %b, %a
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ret i16 %r
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}
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define i32 @func7(i32 %a, i32 %b) {
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; CHECK-LABEL: func7:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.w.sx %s0, %s1, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul i32 %b, %a
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ret i32 %r
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}
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define i64 @func8(i64 %a, i64 %b) {
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; CHECK-LABEL: func8:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.l %s0, %s1, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul i64 %b, %a
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ret i64 %r
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}
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define signext i8 @func9(i8 signext %a) {
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; CHECK-LABEL: func9:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.w.sx %s0, 5, %s0
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; CHECK-NEXT: sla.w.sx %s0, %s0, 24
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; CHECK-NEXT: sra.w.sx %s0, %s0, 24
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul i8 %a, 5
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ret i8 %r
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}
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define signext i16 @func10(i16 signext %a) {
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; CHECK-LABEL: func10:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.w.sx %s0, 5, %s0
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; CHECK-NEXT: sla.w.sx %s0, %s0, 16
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; CHECK-NEXT: sra.w.sx %s0, %s0, 16
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul i16 %a, 5
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ret i16 %r
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}
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define i32 @func11(i32 %a) {
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; CHECK-LABEL: func11:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.w.sx %s0, 5, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul nsw i32 %a, 5
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ret i32 %r
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}
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define i64 @func12(i64 %a) {
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; CHECK-LABEL: func12:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.l %s0, 5, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul nsw i64 %a, 5
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ret i64 %r
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}
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define zeroext i8 @func13(i8 zeroext %a) {
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; CHECK-LABEL: func13:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.w.sx %s0, 5, %s0
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; CHECK-NEXT: and %s0, %s0, (56)0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul i8 %a, 5
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ret i8 %r
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}
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define zeroext i16 @func14(i16 zeroext %a) {
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; CHECK-LABEL: func14:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.w.sx %s0, 5, %s0
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; CHECK-NEXT: and %s0, %s0, (48)0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul i16 %a, 5
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ret i16 %r
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}
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define i32 @func15(i32 %a) {
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; CHECK-LABEL: func15:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.w.sx %s0, 5, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul i32 %a, 5
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ret i32 %r
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}
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define i64 @func16(i64 %a) {
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; CHECK-LABEL: func16:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: muls.l %s0, 5, %s0
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; CHECK-NEXT: or %s11, 0, %s9
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%r = mul i64 %a, 5
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ret i64 %r
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}
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define i32 @func17(i32 %a) {
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; CHECK-LABEL: func17:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: sla.w.sx %s0, %s0, 31
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; CHECK-NEXT: or %s11, 0, %s9
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%r = shl i32 %a, 31
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ret i32 %r
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}
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define i64 @func18(i64 %a) {
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; CHECK-LABEL: func18:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: sll %s0, %s0, 31
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; CHECK-NEXT: or %s11, 0, %s9
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%r = shl nsw i64 %a, 31
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ret i64 %r
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}
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