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llvm-project/llvm/test/CodeGen
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Reid Kleckner 2bcb288ade [codeview] Let the X86 backend tell us the VFRAME offset adjustment 
Use MachineFrameInfo's OffsetAdjustment field to pass this information
from the target to CodeViewDebug.cpp. The X86 backend doesn't use it for
any other purpose.

This fixes PR38857 in the case where there is a non-aligned quantity of
CSRs and a non-aligned quantity of locals.

llvm-svn: 346062
 		2018-11-03 00:41:52 +00:00
..
AArch64 [COFF, ARM64] Implement Intrinsic.sponentry for AArch64 2018-11-01 23:22:25 +00:00
AMDGPU AMDGPU: Fix assertion with bitcast from i64 constant to v4i16 2018-11-02 02:43:55 +00:00
ARC
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ARM ARMExpandPseudoInsts: Fix CMP_SWAP expansion adding a kill flag to a def 2018-11-02 18:22:15 +00:00
AVR [AVR] Fix the 'call.ll' CodeGen test 2018-10-10 03:21:42 +00:00
BPF [bpf] Test case for symbol information in object file 2018-09-22 17:31:01 +00:00
Generic [MIR] Simplify and move MIR test 2018-10-26 16:00:29 +00:00
Hexagon [Hexagon] Do not reduce load size for globals in small-data 2018-11-02 14:17:47 +00:00
Inputs
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Lanai
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MIR [codeview] Let the X86 backend tell us the VFRAME offset adjustment 2018-11-03 00:41:52 +00:00
MSP430
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Mips [DAGCombiner] Remove reduceBuildVecConvertToConvertBuildVec and rely on the vectorizers instead (PR35732) 2018-11-02 11:06:18 +00:00
NVPTX
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Nios2
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PowerPC [PowerPC] Support constraint 'wi' in asm 2018-11-01 02:35:17 +00:00
RISCV [RISCV] Add some missing expansions for floating-point intrinsics 2018-11-02 19:50:38 +00:00
SPARC Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00
SystemZ [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
Thumb [ARM] Add missing pseudo-instruction for Thumb1 RSBS. 2018-10-31 21:45:48 +00:00
Thumb2 [SchedModel] Fix for read advance cycles with implicit pseudo operands. 2018-10-30 15:04:40 +00:00
WebAssembly [WebAssembly] Fix bugs in rethrow depth counting and InstPrinter 2018-11-02 18:38:52 +00:00
WinCFGuard [COFF] Emit @feat.00 on 64-bit and set the CFG bit when emitting guardcf tables 2018-09-19 09:58:30 +00:00
WinEH
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X86 [X86] In LowerEXTEND_VECTOR_INREG, emit a vector shuffle instead of directly using X86ISD::UNPCKL 2018-11-02 22:48:02 +00:00
XCore Relax fast register allocator related test cases; NFC 2018-10-29 20:10:42 +00:00