| .. |
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AsmParser
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[AMDGPU][MC][GFX9] Corrected parsing of v_cndmask_b32_sdwa
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2019-10-18 13:31:53 +00:00 |
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Disassembler
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[AMDGPU][MC][GFX10][WS32] Corrected decoding of dst operand for v_cmp_*_sdwa opcodes
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2019-10-04 13:04:17 +00:00 |
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MCTargetDesc
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[Mips] Use appropriate private label prefix based on Mips ABI
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2019-10-23 12:24:35 +02:00 |
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TargetInfo
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Revert CMake: Make most target symbols hidden by default
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2019-06-11 03:21:13 +00:00 |
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Utils
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AMDGPU: Simplify getAddressSpace calls
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2019-10-31 07:51:38 -07:00 |
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AMDGPU.h
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[AMDGPU] Printf runtime binding pass
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2019-08-12 17:12:29 +00:00 |
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AMDGPU.td
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[AMDGPU] w/a for gfx908 mfma SrcC literal HW bug
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2019-08-23 22:09:58 +00:00 |
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AMDGPUAliasAnalysis.cpp
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AMDGPU: Improve alias analysis for GDS
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2019-07-17 11:22:19 +00:00 |
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AMDGPUAliasAnalysis.h
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…
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AMDGPUAlwaysInlinePass.cpp
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AMDGPU: Simplify getAddressSpace calls
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2019-10-31 07:51:38 -07:00 |
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AMDGPUAnnotateKernelFeatures.cpp
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Use llvm::StringLiteral instead of StringRef in few places
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2019-09-20 14:31:42 +00:00 |
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AMDGPUAnnotateUniformValues.cpp
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…
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AMDGPUArgumentUsageInfo.cpp
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[AMDGPU] Packed thread ids in function call ABI
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2019-06-28 01:52:13 +00:00 |
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AMDGPUArgumentUsageInfo.h
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AMDGPU: Fix Register copypaste error
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2019-09-05 23:07:10 +00:00 |
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AMDGPUAsmPrinter.cpp
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[Alignment] Migrate Attribute::getWith(Stack)Alignment
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2019-10-15 12:56:24 +00:00 |
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AMDGPUAsmPrinter.h
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[AMDGPU] separate accounting for agprs
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2019-10-02 00:26:58 +00:00 |
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AMDGPUAtomicOptimizer.cpp
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[AMDGPU] gfx10 atomic optimizer changes.
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2019-08-23 10:07:43 +00:00 |
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AMDGPUCallLowering.cpp
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[GISel][CallLowering] Make isIncomingArgumentHandler a pure virtual method
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2019-10-18 20:13:42 +00:00 |
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AMDGPUCallLowering.h
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AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC
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2019-09-09 23:06:13 +00:00 |
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AMDGPUCallingConv.td
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[AMDGPU] Adjust number of SGPRs available in Calling Convention
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2019-08-28 15:00:45 +00:00 |
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AMDGPUCodeGenPrepare.cpp
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AMDGPU: Preserve value name when inserting mul24 intrinsic
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2019-08-24 22:17:10 +00:00 |
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AMDGPUFeatures.td
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…
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AMDGPUFixFunctionBitcasts.cpp
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…
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AMDGPUFrameLowering.cpp
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Use Align for TFL::TransientStackAlignment
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2019-10-21 08:31:25 +00:00 |
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AMDGPUFrameLowering.h
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Use Align for TFL::TransientStackAlignment
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2019-10-21 08:31:25 +00:00 |
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AMDGPUGISel.td
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AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG
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2019-10-25 13:11:09 -07:00 |
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AMDGPUGenRegisterBankInfo.def
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AMDGPU/GlobalISel: Fix RegBankSelect for 1024-bit values
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2019-10-02 01:02:14 +00:00 |
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AMDGPUHSAMetadataStreamer.cpp
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[Alignment] Migrate Attribute::getWith(Stack)Alignment
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2019-10-15 12:56:24 +00:00 |
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AMDGPUHSAMetadataStreamer.h
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[llvm] Migrate llvm::make_unique to std::make_unique
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2019-08-15 15:54:37 +00:00 |
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AMDGPUISelDAGToDAG.cpp
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AMDGPU: Slightly restructure m0 init code
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2019-10-21 19:42:26 +00:00 |
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AMDGPUISelLowering.cpp
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AMDGPU: Select basic interp directly from intrinsics
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2019-10-21 21:49:44 +00:00 |
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AMDGPUISelLowering.h
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AMDGPU: Select basic interp directly from intrinsics
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2019-10-21 21:49:44 +00:00 |
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AMDGPUInline.cpp
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[AMDGPU] Improve code size cost model
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2019-10-17 12:15:35 +00:00 |
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AMDGPUInstrInfo.cpp
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…
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AMDGPUInstrInfo.h
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…
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AMDGPUInstrInfo.td
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AMDGPU: Select basic interp directly from intrinsics
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2019-10-21 21:49:44 +00:00 |
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AMDGPUInstructionSelector.cpp
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AMDGPU: Relax 32-bit SGPR register class
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2019-10-18 18:26:37 +00:00 |
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AMDGPUInstructionSelector.h
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AMDGPU/GlobalISel: Select s1 src G_SITOFP/G_UITOFP
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2019-10-01 02:23:20 +00:00 |
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AMDGPUInstructions.td
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AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG
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2019-10-25 13:11:09 -07:00 |
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AMDGPULegalizerInfo.cpp
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AMDGPU/GlobalISel: Legalize FDIV32
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2019-10-29 17:18:06 -07:00 |
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AMDGPULegalizerInfo.h
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AMDGPU/GlobalISel: Legalize FDIV32
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2019-10-29 17:18:06 -07:00 |
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AMDGPULibCalls.cpp
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[NFC] Remove redundant lines
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2019-10-24 19:54:28 +03:00 |
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AMDGPULibFunc.cpp
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[AMDGPU] Downgrade from StringLiteral to const char* in an attempt to make GCC 5 happy
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2019-08-25 12:47:31 +00:00 |
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AMDGPULibFunc.h
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…
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AMDGPULowerIntrinsics.cpp
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…
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AMDGPULowerKernelArguments.cpp
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[Alignment] Migrate Attribute::getWith(Stack)Alignment
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2019-10-15 12:56:24 +00:00 |
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AMDGPULowerKernelAttributes.cpp
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…
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AMDGPUMCInstLower.cpp
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[AMDGPU] link dpp pseudos and real instructions on gfx10
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2019-10-11 22:03:36 +00:00 |
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AMDGPUMachineCFGStructurizer.cpp
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Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-15 19:22:08 +00:00 |
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AMDGPUMachineFunction.cpp
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[Alignment] Migrate Attribute::getWith(Stack)Alignment
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2019-10-15 12:56:24 +00:00 |
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AMDGPUMachineFunction.h
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[Alignment] Migrate Attribute::getWith(Stack)Alignment
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2019-10-15 12:56:24 +00:00 |
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AMDGPUMachineModuleInfo.cpp
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…
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AMDGPUMachineModuleInfo.h
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…
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AMDGPUMacroFusion.cpp
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…
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AMDGPUMacroFusion.h
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…
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AMDGPUOpenCLEnqueuedBlockLowering.cpp
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Fix parameter name comments using clang-tidy. NFC.
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2019-07-16 04:46:31 +00:00 |
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AMDGPUPTNote.h
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…
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AMDGPUPerfHintAnalysis.cpp
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AMDGPU: Fix assert in clang test
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2019-07-05 21:09:53 +00:00 |
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AMDGPUPerfHintAnalysis.h
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AMDGPU: Make AMDGPUPerfHintAnalysis an SCC pass
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2019-07-05 20:26:13 +00:00 |
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AMDGPUPrintfRuntimeBinding.cpp
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[AMDGPU] Make printf lowering faster when there are no printfs
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2019-10-02 08:44:15 +00:00 |
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AMDGPUPromoteAlloca.cpp
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AMDGPU: Simplify getAddressSpace calls
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2019-10-31 07:51:38 -07:00 |
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AMDGPUPropagateAttributes.cpp
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AMDGPU: Move DEBUG_TYPE definition below includes
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2019-07-08 18:48:39 +00:00 |
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AMDGPURegisterBankInfo.cpp
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AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG
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2019-10-25 13:11:09 -07:00 |
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AMDGPURegisterBankInfo.h
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AMDGPU/GlobalISel: Split 64-bit vector extracts during RegBankSelect
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2019-10-03 17:55:27 +00:00 |
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AMDGPURegisterBanks.td
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AMDGPU/GlobalISel: Increase max legal size to 1024
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2019-10-01 16:35:06 +00:00 |
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AMDGPURegisterInfo.cpp
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AMDGPU/GlobalISel: Handle more G_INSERT cases
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2019-10-07 19:16:26 +00:00 |
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AMDGPURegisterInfo.h
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AMDGPU/GlobalISel: Handle more G_INSERT cases
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2019-10-07 19:16:26 +00:00 |
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AMDGPURegisterInfo.td
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[AMDGPU] gfx908 register file changes
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2019-07-09 19:41:51 +00:00 |
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AMDGPURewriteOutArguments.cpp
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…
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AMDGPUSearchableTables.td
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AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec}
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2019-08-05 09:36:06 +00:00 |
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AMDGPUSubtarget.cpp
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[AMDGPU] Fix mfma scheduling crash
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2019-10-24 11:01:52 -07:00 |
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AMDGPUSubtarget.h
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[Alignment][NFC] Use Align for TargetFrameLowering/Subtarget
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2019-10-17 07:49:39 +00:00 |
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AMDGPUTargetMachine.cpp
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Revert "[AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs."
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2019-10-10 13:34:31 +00:00 |
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AMDGPUTargetMachine.h
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…
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AMDGPUTargetObjectFile.cpp
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…
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AMDGPUTargetObjectFile.h
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…
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AMDGPUTargetTransformInfo.cpp
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[AMDGPU] Improve code size cost model
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2019-10-17 12:15:35 +00:00 |
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AMDGPUTargetTransformInfo.h
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[AMDGPU] Improve code size cost model
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2019-10-17 12:15:35 +00:00 |
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AMDGPUUnifyDivergentExitNodes.cpp
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Update phis in AMDGPUUnifyDivergentExitNodes
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2019-06-25 18:55:16 +00:00 |
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AMDGPUUnifyMetadata.cpp
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…
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AMDILCFGStructurizer.cpp
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Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-15 19:22:08 +00:00 |
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AMDKernelCodeT.h
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[AMDGPU] gfx1010 wave32 metadata
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2019-06-17 16:48:56 +00:00 |
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BUFInstructions.td
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[AMDGPU] drop getIsFP td helper
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2019-10-17 21:46:56 +00:00 |
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CMakeLists.txt
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[AMDGPU] Printf runtime binding pass
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2019-08-12 17:12:29 +00:00 |
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CaymanInstructions.td
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…
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DSInstructions.td
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[AMDGPU][MC][GFX9][GFX10] Corrected number of src operands for ds_[read/write]_addtid_b32
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2019-10-11 14:53:26 +00:00 |
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EvergreenInstructions.td
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AMDGPU: Start redefining atomic PatFrags
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2019-08-01 03:25:52 +00:00 |
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FLATInstructions.td
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AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG
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2019-10-25 13:11:09 -07:00 |
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GCNDPPCombine.cpp
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[AMDGPU] Disallow dpp combining for dpp instructions without Src2 operand (when Src2 is required)
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2019-10-25 21:30:37 +03:00 |
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GCNHazardRecognizer.cpp
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AMDGPU: Fix SMEM WAR hazard for gfx10 readlane
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2019-10-18 18:20:30 +00:00 |
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GCNHazardRecognizer.h
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[AMDGPU] gfx908 hazard recognizer
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2019-07-11 21:30:34 +00:00 |
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GCNILPSched.cpp
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Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each
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2019-10-19 01:31:09 +00:00 |
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GCNIterativeScheduler.cpp
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[llvm] Migrate llvm::make_unique to std::make_unique
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2019-08-15 15:54:37 +00:00 |
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GCNIterativeScheduler.h
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…
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GCNMinRegStrategy.cpp
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…
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GCNNSAReassign.cpp
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Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-15 19:22:08 +00:00 |
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GCNProcessors.td
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[AMDGPU] gfx908 target
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2019-07-09 18:10:06 +00:00 |
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GCNRegBankReassign.cpp
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Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-15 19:22:08 +00:00 |
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GCNRegPressure.cpp
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Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-15 19:22:08 +00:00 |
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GCNRegPressure.h
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Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
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2019-08-01 23:27:28 +00:00 |
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GCNSchedStrategy.cpp
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[AMDGPU] Add VerifyScheduling support.
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2019-10-01 15:45:47 +00:00 |
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GCNSchedStrategy.h
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AMDGPU: Avoid constructing new std::vector in initCandidate
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2019-09-05 22:44:06 +00:00 |
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LLVMBuild.txt
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[AMDGPU] Move InstPrinter files to MCTargetDesc. NFC
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2019-05-11 00:03:35 +00:00 |
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MIMGInstructions.td
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[AMDGPU] Use PredicateControl in MIMGBaseOpcode. NFC.
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2019-08-12 22:32:21 +00:00 |
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R600.td
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…
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R600AsmPrinter.cpp
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[Alignment][NFC] Remove unneeded llvm:: scoping on Align types
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2019-09-27 12:54:21 +00:00 |
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R600AsmPrinter.h
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…
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R600ClauseMergePass.cpp
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…
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R600ControlFlowFinalizer.cpp
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Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-15 19:22:08 +00:00 |
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R600Defines.h
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…
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R600EmitClauseMarkers.cpp
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…
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R600ExpandSpecialInstrs.cpp
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Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-15 19:22:08 +00:00 |
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R600FrameLowering.cpp
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…
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R600FrameLowering.h
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Use Align for TFL::TransientStackAlignment
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2019-10-21 08:31:25 +00:00 |
|
R600ISelLowering.cpp
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[AMDGPU] Use math constants defined in MathExtras (NFC)
|
2019-10-09 20:00:43 +00:00 |
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R600ISelLowering.h
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[TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR42123)
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2019-06-12 17:14:03 +00:00 |
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R600InstrFormats.td
|
…
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R600InstrInfo.cpp
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Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-15 19:22:08 +00:00 |
|
R600InstrInfo.h
|
…
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|
R600Instructions.td
|
AMDGPU: Redefine load PatFrags
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2019-07-16 17:38:50 +00:00 |
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R600MachineFunctionInfo.cpp
|
…
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R600MachineFunctionInfo.h
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…
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R600MachineScheduler.cpp
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Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
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2019-08-15 19:22:08 +00:00 |
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R600MachineScheduler.h
|
…
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|
|
R600OpenCLImageTypeLoweringPass.cpp
|
…
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|
R600OptimizeVectorRegisters.cpp
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
|
2019-08-15 19:22:08 +00:00 |
|
R600Packetizer.cpp
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
|
2019-08-15 19:22:08 +00:00 |
|
R600Processors.td
|
…
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|
|
R600RegisterInfo.cpp
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Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
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2019-08-01 23:27:28 +00:00 |
|
R600RegisterInfo.h
|
CodeGen: Introduce a class for registers
|
2019-06-24 15:50:29 +00:00 |
|
R600RegisterInfo.td
|
…
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|
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R600Schedule.td
|
…
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|
|
R700Instructions.td
|
…
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|
|
SIAddIMGInit.cpp
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
|
2019-08-15 19:22:08 +00:00 |
|
SIAnnotateControlFlow.cpp
|
[AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32
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2019-06-13 23:47:36 +00:00 |
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SIDefines.h
|
[AMDGPU] Added MI bit IsDOT
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2019-09-17 17:56:13 +00:00 |
|
SIFixSGPRCopies.cpp
|
[AMDGPU] move PHI nodes to AGPR class
|
2019-10-18 22:48:45 +00:00 |
|
SIFixVGPRCopies.cpp
|
…
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|
|
SIFixupVectorISel.cpp
|
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
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2019-08-01 23:27:28 +00:00 |
|
SIFoldOperands.cpp
|
[AMDGPU] Enable SGPR copy folding
|
2019-10-25 15:08:30 -07:00 |
|
SIFormMemoryClauses.cpp
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
|
2019-08-15 19:22:08 +00:00 |
|
SIFrameLowering.cpp
|
[AArch64] Static (de)allocation of SVE stack objects.
|
2019-10-03 11:33:50 +00:00 |
|
SIFrameLowering.h
|
Use Align for TFL::TransientStackAlignment
|
2019-10-21 08:31:25 +00:00 |
|
SIISelLowering.cpp
|
AMDGPU: Simplify getAddressSpace calls
|
2019-10-31 07:51:38 -07:00 |
|
SIISelLowering.h
|
AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG
|
2019-10-25 13:11:09 -07:00 |
|
SIInsertSkips.cpp
|
[AMDGPU] gfx10 conditional registers handling
|
2019-06-16 17:13:09 +00:00 |
|
SIInsertWaitcnts.cpp
|
[AMDGPU] Simplify VCCZ bug handling
|
2019-10-30 17:09:07 +00:00 |
|
SIInstrFormats.td
|
[AMDGPU] Added MI bit IsDOT
|
2019-09-17 17:56:13 +00:00 |
|
SIInstrInfo.cpp
|
AMDGPU: Disallow spill folding with m0 copies
|
2019-10-30 14:56:33 -07:00 |
|
SIInstrInfo.h
|
AMDGPU: Disallow spill folding with m0 copies
|
2019-10-30 14:56:33 -07:00 |
|
SIInstrInfo.td
|
AMDGPU: Fix missing OPERAND_IMMEDIATE
|
2019-10-20 16:56:10 +00:00 |
|
SIInstructions.td
|
AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG
|
2019-10-25 13:11:09 -07:00 |
|
SILoadStoreOptimizer.cpp
|
[AMDGPU] Extend the SI Load/Store optimizer
|
2019-10-16 10:17:02 +00:00 |
|
SILowerControlFlow.cpp
|
[AMDGPU]: PHI Elimination hooks added for custom COPY insertion. Fixed
|
2019-09-17 09:08:58 +00:00 |
|
SILowerI1Copies.cpp
|
[AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies.
|
2019-10-26 14:37:45 +05:30 |
|
SILowerSGPRSpills.cpp
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
|
2019-08-15 19:22:08 +00:00 |
|
SIMachineFunctionInfo.cpp
|
[Alignment] Migrate Attribute::getWith(Stack)Alignment
|
2019-10-15 12:56:24 +00:00 |
|
SIMachineFunctionInfo.h
|
AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization
|
2019-08-27 18:18:38 +00:00 |
|
SIMachineScheduler.cpp
|
[llvm] Migrate llvm::make_unique to std::make_unique
|
2019-08-15 15:54:37 +00:00 |
|
SIMachineScheduler.h
|
…
|
|
|
SIMemoryLegalizer.cpp
|
[llvm] Migrate llvm::make_unique to std::make_unique
|
2019-08-15 15:54:37 +00:00 |
|
SIModeRegister.cpp
|
[llvm] Migrate llvm::make_unique to std::make_unique
|
2019-08-15 15:54:37 +00:00 |
|
SIOptimizeExecMasking.cpp
|
Revert "AMDGPU: Fix iterator error when lowering SI_END_CF"
|
2019-08-20 17:45:25 +00:00 |
|
SIOptimizeExecMaskingPreRA.cpp
|
AMDGPU: Propagate undef flag during pre-RA exec mask optimizations
|
2019-10-08 12:46:32 +00:00 |
|
SIPeepholeSDWA.cpp
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
|
2019-08-15 19:22:08 +00:00 |
|
SIPreAllocateWWMRegs.cpp
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
|
2019-08-15 19:22:08 +00:00 |
|
SIProgramInfo.h
|
[AMDGPU] separate accounting for agprs
|
2019-10-02 00:26:58 +00:00 |
|
SIRegisterInfo.cpp
|
Fix buildbot error in SIRegisterInfo.cpp.
|
2019-10-20 20:01:16 +00:00 |
|
SIRegisterInfo.h
|
[AMDGPU] Remove -amdgpu-spill-sgpr-to-smem.
|
2019-10-18 21:48:22 +00:00 |
|
SIRegisterInfo.td
|
AMDGPU: Make VReg_1 only include 1 artificial register
|
2019-10-28 20:51:51 -07:00 |
|
SISchedule.td
|
[AMDGPU] gfx908 scheduling
|
2019-07-11 21:25:00 +00:00 |
|
SIShrinkInstructions.cpp
|
AMDGPU: Don't fold S_NOPs with implicit operands
|
2019-10-30 14:40:56 -07:00 |
|
SIWholeQuadMode.cpp
|
Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM
|
2019-08-15 19:22:08 +00:00 |
|
SMInstructions.td
|
AMDGPU/GlobalISel: Select SMRD loads for more types
|
2019-09-16 00:54:07 +00:00 |
|
SOPInstructions.td
|
AMDGPU/GlobalISel: Allow selection of scalar min/max
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2019-09-21 02:37:33 +00:00 |
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VIInstrFormats.td
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VIInstructions.td
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VOP1Instructions.td
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[AMDGPU] Supress unused sdwa insts generation
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2019-10-16 16:58:06 +00:00 |
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VOP2Instructions.td
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[AMDGPU][MC][GFX10] Added sdwa/dpp versions of v_cndmask_b32
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2019-10-18 14:49:53 +00:00 |
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VOP3Instructions.td
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[AMDGPU][MC][GFX10] Added v_interp_[p1/p2/mov]_f32_e64
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2019-10-28 15:03:43 +03:00 |
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VOP3PInstructions.td
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[AMDGPU] Added MI bit IsDOT
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2019-09-17 17:56:13 +00:00 |
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VOPCInstructions.td
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[AMDGPU] Supress unused sdwa insts generation
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2019-10-16 16:58:06 +00:00 |
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VOPInstructions.td
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[AMDGPU] copy OtherPredicates from pseudo to VOP3_Real
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2019-09-26 21:06:17 +00:00 |
bc56166281