Guillaume Chatelet ad1cea0dda [Alignment][NFC] Use Align with TargetLowering::setPrefFunctionAlignment ... Summary: This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: nemanjai, javed.absar, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, s.egerton, pzheng, ychen, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67267 llvm-svn: 371212		2019-09-06 15:03:49 +00:00
..
AsmParser	Do a sweep of symbol internalization. NFC.	2019-08-23 19:59:23 +00:00
Disassembler	[RISCV] Remove fix introduced by r369573, superseded by r369580	2019-08-21 22:02:56 +00:00
MCTargetDesc	[MC] Minor cleanup to MCFixup::Kind handling. NFC.	2019-08-23 01:00:55 +00:00
TargetInfo	Revert CMake: Make most target symbols hidden by default	2019-06-11 03:21:13 +00:00
Utils	[RISCV] Avoid signed integer overflow UB in RISCVMatInt::generateInstSeq	2019-07-18 04:02:58 +00:00
CMakeLists.txt	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
LLVMBuild.txt	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCV.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCV.td	[RISCV] Add support for RVC HINT instructions	2019-08-21 14:00:58 +00:00
RISCVAsmPrinter.cpp	[RISCV] Support z and i operand modifiers	2019-07-08 05:00:26 +00:00
RISCVCallLowering.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVCallLowering.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVCallingConv.td	[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs	2019-03-30 17:59:30 +00:00
RISCVExpandPseudoInsts.cpp	[RISCV] Convert registers from unsigned to Register	2019-08-16 14:27:50 +00:00
RISCVFrameLowering.cpp	[RISCV] Convert registers from unsigned to Register	2019-08-16 14:27:50 +00:00
RISCVFrameLowering.h	[RISCV] Convert registers from unsigned to Register	2019-08-16 14:27:50 +00:00
RISCVISelDAGToDAG.cpp	[RISCV] Lower inline asm constraint A for RISC-V	2019-08-16 10:28:34 +00:00
RISCVISelLowering.cpp	[Alignment][NFC] Use Align with TargetLowering::setPrefFunctionAlignment	2019-09-06 15:03:49 +00:00
RISCVISelLowering.h	[RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall	2019-08-28 23:40:37 +00:00
RISCVInstrFormats.td	[RISCV] Implement pseudo instructions for load/store from a symbol address.	2019-02-20 03:31:32 +00:00
RISCVInstrFormatsC.td	Update the file headers across all of the LLVM projects in the monorepo	2019-01-19 08:50:56 +00:00
RISCVInstrInfo.cpp	[RISCV] Convert registers from unsigned to Register	2019-08-16 14:27:50 +00:00
RISCVInstrInfo.h	[RISCV] Convert registers from unsigned to Register	2019-08-16 14:27:50 +00:00
RISCVInstrInfo.td	[RISCV] Add support for RVC HINT instructions	2019-08-21 14:00:58 +00:00
RISCVInstrInfoA.td	[RISCV] Add Custom Parser for Atomic Memory Operands	2019-08-01 12:42:31 +00:00
RISCVInstrInfoC.td	[RISCV] Add support for RVC HINT instructions	2019-08-21 14:00:58 +00:00
RISCVInstrInfoD.td	[RISCV] Add seto pattern expansion	2019-04-01 09:54:14 +00:00
RISCVInstrInfoF.td	[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references	2019-07-05 12:16:40 +00:00
RISCVInstrInfoM.td	[RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M	2019-01-25 05:11:34 +00:00
RISCVInstructionSelector.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVLegalizerInfo.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVMCInstLower.cpp	[RISCV] Add lowering of global TLS addresses	2019-06-19 08:40:59 +00:00
RISCVMachineFunctionInfo.h	[RISCV] Delete a ctor that is commented out. NFC	2019-07-05 08:25:14 +00:00
RISCVMergeBaseOffset.cpp	[RISCV] Convert registers from unsigned to Register	2019-08-16 14:27:50 +00:00
RISCVRegisterBankInfo.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVRegisterBankInfo.h	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVRegisterBanks.td	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVRegisterInfo.cpp	[risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-12 22:41:02 +00:00
RISCVRegisterInfo.h	[RISCV] Implement RISCVRegisterInfo::getPointerRegClass	2019-08-27 21:37:57 +00:00
RISCVRegisterInfo.td	[RISCV] Add support for RVC HINT instructions	2019-08-21 14:00:58 +00:00
RISCVSubtarget.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVSubtarget.h	[RISCV] Add support for RVC HINT instructions	2019-08-21 14:00:58 +00:00
RISCVSystemOperands.td	[RISCV][NFC] Replace hard-coded CSR duplication with symbolic references	2019-07-05 12:16:40 +00:00
RISCVTargetMachine.cpp	[RISCV GlobalISel] Adding initial GlobalISel infrastructure	2019-08-20 22:53:24 +00:00
RISCVTargetMachine.h	[RISCV] Add RISCV-specific TargetTransformInfo	2019-06-21 13:36:09 +00:00
RISCVTargetObjectFile.cpp	[RISCV] Put data smaller than eight bytes to small data section	2019-04-11 04:59:13 +00:00
RISCVTargetObjectFile.h	[RISCV] Put data smaller than eight bytes to small data section	2019-04-11 04:59:13 +00:00
RISCVTargetTransformInfo.cpp	[RISCV] Fix RISCVTTIImpl::getIntImmCost for immediates where getMinSignedBits() > 64	2019-07-09 10:56:18 +00:00
RISCVTargetTransformInfo.h	[RISCV] Add RISCV-specific TargetTransformInfo	2019-06-21 13:36:09 +00:00