forked from OSchip/llvm-project
47 lines
1.7 KiB
TableGen
47 lines
1.7 KiB
TableGen
//===- Lanai.td - Describe the Lanai Target Machine --------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// Register File, Calling Conv, Instruction Descriptions
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//===----------------------------------------------------------------------===//
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include "LanaiSchedule.td"
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include "LanaiRegisterInfo.td"
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include "LanaiCallingConv.td"
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include "LanaiInstrInfo.td"
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def LanaiInstrInfo : InstrInfo;
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//===----------------------------------------------------------------------===//
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// Lanai processors supported.
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//===----------------------------------------------------------------------===//
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def : ProcessorModel<"generic", LanaiSchedModel, []>;
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def : ProcessorModel<"v11", LanaiSchedModel, []>;
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def LanaiInstPrinter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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bit isMCAsmWriter = 1;
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}
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//===----------------------------------------------------------------------===//
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def Lanai : Target {
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// Pull in Instruction Info:
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let InstructionSet = LanaiInstrInfo;
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let AssemblyWriters = [LanaiInstPrinter];
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}
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