forked from OSchip/llvm-project
01aefae4a1
Summary: If a user writing C code using the ACLE MVE intrinsics generates a predicate and then complements it, then the resulting IR will use the `pred_v2i` IR intrinsic to turn some `<n x i1>` vector into a 16-bit integer; complement that integer; and convert back. This will generate machine code that moves the predicate out of the `P0` register, complements it in an integer GPR, and moves it back in again. This InstCombine rule replaces `i2v(~v2i(x))` with a direct complement of the original predicate vector, which we can already instruction- select as the VPNOT instruction which complements P0 in place. Reviewers: ostannard, MarkMurrayARM, dmgreen Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70484 |
||
|---|---|---|
| .. | ||
| 2012-04-23-Neon-Intrinsics.ll | ||
| aes-intrinsics.ll | ||
| constant-fold-hang.ll | ||
| lit.local.cfg | ||
| mve-v2i2v.ll | ||
| neon-intrinsics.ll | ||
| strcmp.ll | ||
| strcpy.ll | ||
| tbl1.ll | ||
| vld1.ll | ||