forked from OSchip/llvm-project
411 lines
20 KiB
TableGen
411 lines
20 KiB
TableGen
//===-- X86InstrXOP.td - XOP Instruction Set ---------------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes XOP (eXtended OPerations)
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//
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//===----------------------------------------------------------------------===//
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multiclass xop2op<bits<8> opc, string OpcodeStr, Intrinsic Int, PatFrag memop> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int VR128:$src))]>, XOP;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
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}
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let ExeDomain = SSEPackedInt in {
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defm VPHSUBWD : xop2op<0xE2, "vphsubwd", int_x86_xop_vphsubwd, loadv2i64>;
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defm VPHSUBDQ : xop2op<0xE3, "vphsubdq", int_x86_xop_vphsubdq, loadv2i64>;
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defm VPHSUBBW : xop2op<0xE1, "vphsubbw", int_x86_xop_vphsubbw, loadv2i64>;
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defm VPHADDWQ : xop2op<0xC7, "vphaddwq", int_x86_xop_vphaddwq, loadv2i64>;
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defm VPHADDWD : xop2op<0xC6, "vphaddwd", int_x86_xop_vphaddwd, loadv2i64>;
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defm VPHADDUWQ : xop2op<0xD7, "vphadduwq", int_x86_xop_vphadduwq, loadv2i64>;
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defm VPHADDUWD : xop2op<0xD6, "vphadduwd", int_x86_xop_vphadduwd, loadv2i64>;
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defm VPHADDUDQ : xop2op<0xDB, "vphaddudq", int_x86_xop_vphaddudq, loadv2i64>;
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defm VPHADDUBW : xop2op<0xD1, "vphaddubw", int_x86_xop_vphaddubw, loadv2i64>;
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defm VPHADDUBQ : xop2op<0xD3, "vphaddubq", int_x86_xop_vphaddubq, loadv2i64>;
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defm VPHADDUBD : xop2op<0xD2, "vphaddubd", int_x86_xop_vphaddubd, loadv2i64>;
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defm VPHADDDQ : xop2op<0xCB, "vphadddq", int_x86_xop_vphadddq, loadv2i64>;
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defm VPHADDBW : xop2op<0xC1, "vphaddbw", int_x86_xop_vphaddbw, loadv2i64>;
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defm VPHADDBQ : xop2op<0xC3, "vphaddbq", int_x86_xop_vphaddbq, loadv2i64>;
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defm VPHADDBD : xop2op<0xC2, "vphaddbd", int_x86_xop_vphaddbd, loadv2i64>;
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}
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// Scalar load 2 addr operand instructions
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multiclass xop2opsld<bits<8> opc, string OpcodeStr, Intrinsic Int,
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Operand memop, ComplexPattern mem_cpat> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int VR128:$src))]>, XOP;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins memop:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int (bitconvert mem_cpat:$src)))]>, XOP;
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}
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multiclass xop2op128<bits<8> opc, string OpcodeStr, Intrinsic Int,
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PatFrag memop> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int VR128:$src))]>, XOP;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR128:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP;
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}
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multiclass xop2op256<bits<8> opc, string OpcodeStr, Intrinsic Int,
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PatFrag memop> {
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def rrY : IXOP<opc, MRMSrcReg, (outs VR256:$dst), (ins VR256:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (Int VR256:$src))]>, XOP, VEX_L;
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def rmY : IXOP<opc, MRMSrcMem, (outs VR256:$dst), (ins f256mem:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set VR256:$dst, (Int (bitconvert (memop addr:$src))))]>, XOP, VEX_L;
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}
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let ExeDomain = SSEPackedSingle in {
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defm VFRCZSS : xop2opsld<0x82, "vfrczss", int_x86_xop_vfrcz_ss,
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ssmem, sse_load_f32>;
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defm VFRCZPS : xop2op128<0x80, "vfrczps", int_x86_xop_vfrcz_ps, loadv4f32>;
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defm VFRCZPS : xop2op256<0x80, "vfrczps", int_x86_xop_vfrcz_ps_256, loadv8f32>;
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}
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let ExeDomain = SSEPackedDouble in {
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defm VFRCZSD : xop2opsld<0x83, "vfrczsd", int_x86_xop_vfrcz_sd,
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sdmem, sse_load_f64>;
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defm VFRCZPD : xop2op128<0x81, "vfrczpd", int_x86_xop_vfrcz_pd, loadv2f64>;
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defm VFRCZPD : xop2op256<0x81, "vfrczpd", int_x86_xop_vfrcz_pd_256, loadv4f64>;
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}
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multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType vt128> {
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def rr : IXOP<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2))))]>,
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XOP_4VOp3, Sched<[WriteVarVecShift]>;
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def rm : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1),
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(vt128 (bitconvert (loadv2i64 addr:$src2))))))]>,
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XOP_4V, VEX_W, Sched<[WriteVarVecShift, ReadAfterLd]>;
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def mr : IXOP<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))),
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(vt128 VR128:$src2))))]>,
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XOP_4VOp3, Sched<[WriteVarVecShift, ReadAfterLd]>;
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}
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let ExeDomain = SSEPackedInt in {
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defm VPROTB : xop3op<0x90, "vprotb", X86vprot, v16i8>;
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defm VPROTD : xop3op<0x92, "vprotd", X86vprot, v4i32>;
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defm VPROTQ : xop3op<0x93, "vprotq", X86vprot, v2i64>;
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defm VPROTW : xop3op<0x91, "vprotw", X86vprot, v8i16>;
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defm VPSHAB : xop3op<0x98, "vpshab", X86vpsha, v16i8>;
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defm VPSHAD : xop3op<0x9A, "vpshad", X86vpsha, v4i32>;
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defm VPSHAQ : xop3op<0x9B, "vpshaq", X86vpsha, v2i64>;
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defm VPSHAW : xop3op<0x99, "vpshaw", X86vpsha, v8i16>;
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defm VPSHLB : xop3op<0x94, "vpshlb", X86vpshl, v16i8>;
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defm VPSHLD : xop3op<0x96, "vpshld", X86vpshl, v4i32>;
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defm VPSHLQ : xop3op<0x97, "vpshlq", X86vpshl, v2i64>;
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defm VPSHLW : xop3op<0x95, "vpshlw", X86vpshl, v8i16>;
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}
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multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType vt128> {
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def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, u8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>, XOP;
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def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins i128mem:$src1, u8imm:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 (bitconvert (loadv2i64 addr:$src1))), imm:$src2)))]>, XOP;
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}
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let ExeDomain = SSEPackedInt in {
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defm VPROTB : xop3opimm<0xC0, "vprotb", X86vproti, v16i8>;
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defm VPROTD : xop3opimm<0xC2, "vprotd", X86vproti, v4i32>;
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defm VPROTQ : xop3opimm<0xC3, "vprotq", X86vproti, v2i64>;
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defm VPROTW : xop3opimm<0xC1, "vprotw", X86vproti, v8i16>;
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}
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// Instruction where second source can be memory, but third must be register
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multiclass xop4opm2<bits<8> opc, string OpcodeStr, Intrinsic Int> {
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let isCommutable = 1 in
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def rr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, VR128:$src2, VR128:$src3))]>, XOP_4V, VEX_I8IMM;
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def rm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
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VR128:$src3))]>, XOP_4V, VEX_I8IMM;
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}
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let ExeDomain = SSEPackedInt in {
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defm VPMADCSWD : xop4opm2<0xB6, "vpmadcswd", int_x86_xop_vpmadcswd>;
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defm VPMADCSSWD : xop4opm2<0xA6, "vpmadcsswd", int_x86_xop_vpmadcsswd>;
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defm VPMACSWW : xop4opm2<0x95, "vpmacsww", int_x86_xop_vpmacsww>;
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defm VPMACSWD : xop4opm2<0x96, "vpmacswd", int_x86_xop_vpmacswd>;
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defm VPMACSSWW : xop4opm2<0x85, "vpmacssww", int_x86_xop_vpmacssww>;
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defm VPMACSSWD : xop4opm2<0x86, "vpmacsswd", int_x86_xop_vpmacsswd>;
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defm VPMACSSDQL : xop4opm2<0x87, "vpmacssdql", int_x86_xop_vpmacssdql>;
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defm VPMACSSDQH : xop4opm2<0x8F, "vpmacssdqh", int_x86_xop_vpmacssdqh>;
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defm VPMACSSDD : xop4opm2<0x8E, "vpmacssdd", int_x86_xop_vpmacssdd>;
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defm VPMACSDQL : xop4opm2<0x97, "vpmacsdql", int_x86_xop_vpmacsdql>;
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defm VPMACSDQH : xop4opm2<0x9F, "vpmacsdqh", int_x86_xop_vpmacsdqh>;
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defm VPMACSDD : xop4opm2<0x9E, "vpmacsdd", int_x86_xop_vpmacsdd>;
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}
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// Instruction where second source can be memory, third must be imm8
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multiclass xopvpcom<bits<8> opc, string Suffix, SDNode OpNode, ValueType vt128> {
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let isCommutable = 1 in
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def ri : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, XOPCC:$cc),
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!strconcat("vpcom${cc}", Suffix,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
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i8immZExt3:$cc)))]>,
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XOP_4V;
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def mi : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, XOPCC:$cc),
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!strconcat("vpcom${cc}", Suffix,
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"\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1),
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(vt128 (bitconvert (loadv2i64 addr:$src2))),
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i8immZExt3:$cc)))]>,
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XOP_4V;
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let isAsmParserOnly = 1, hasSideEffects = 0 in {
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def ri_alt : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, u8imm:$src3),
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!strconcat("vpcom", Suffix,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_4V;
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let mayLoad = 1 in
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def mi_alt : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, u8imm:$src3),
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!strconcat("vpcom", Suffix,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_4V;
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}
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}
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let ExeDomain = SSEPackedInt in { // SSE integer instructions
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defm VPCOMB : xopvpcom<0xCC, "b", X86vpcom, v16i8>;
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defm VPCOMW : xopvpcom<0xCD, "w", X86vpcom, v8i16>;
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defm VPCOMD : xopvpcom<0xCE, "d", X86vpcom, v4i32>;
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defm VPCOMQ : xopvpcom<0xCF, "q", X86vpcom, v2i64>;
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defm VPCOMUB : xopvpcom<0xEC, "ub", X86vpcomu, v16i8>;
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defm VPCOMUW : xopvpcom<0xED, "uw", X86vpcomu, v8i16>;
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defm VPCOMUD : xopvpcom<0xEE, "ud", X86vpcomu, v4i32>;
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defm VPCOMUQ : xopvpcom<0xEF, "uq", X86vpcomu, v2i64>;
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}
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multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType vt128> {
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def rrr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
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(vt128 VR128:$src3))))]>,
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XOP_4V, VEX_I8IMM;
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def rrm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i128mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
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(vt128 (bitconvert (loadv2i64 addr:$src3))))))]>,
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XOP_4V, VEX_I8IMM, VEX_W, MemOp4;
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def rmr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(v16i8 (OpNode (vt128 VR128:$src1), (vt128 (bitconvert (loadv2i64 addr:$src2))),
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(vt128 VR128:$src3))))]>,
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XOP_4V, VEX_I8IMM;
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// For disassembler
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
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def rrr_REV : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[]>, XOP_4V, VEX_I8IMM, VEX_W, MemOp4;
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}
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let ExeDomain = SSEPackedInt in {
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defm VPPERM : xop4op<0xA3, "vpperm", X86vpperm, v16i8>;
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}
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// Instruction where either second or third source can be memory
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multiclass xop4op_int<bits<8> opc, string OpcodeStr,
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Intrinsic Int128, Intrinsic Int256> {
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// 128-bit Instruction
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def rrr : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst, (Int128 VR128:$src1, VR128:$src2, VR128:$src3))]>,
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XOP_4V, VEX_I8IMM;
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def rrm : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i128mem:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int128 VR128:$src1, VR128:$src2,
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(bitconvert (loadv2i64 addr:$src3))))]>,
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XOP_4V, VEX_I8IMM, VEX_W, MemOp4;
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def rmr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
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[(set VR128:$dst,
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(Int128 VR128:$src1, (bitconvert (loadv2i64 addr:$src2)),
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VR128:$src3))]>,
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XOP_4V, VEX_I8IMM;
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// For disassembler
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
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def rrr_REV : IXOPi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, VR128:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
|
[]>, XOP_4V, VEX_I8IMM, VEX_W, MemOp4;
|
|
|
|
// 256-bit Instruction
|
|
def rrrY : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
|
|
(ins VR256:$src1, VR256:$src2, VR256:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
|
[(set VR256:$dst, (Int256 VR256:$src1, VR256:$src2, VR256:$src3))]>,
|
|
XOP_4V, VEX_I8IMM, VEX_L;
|
|
def rrmY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
|
|
(ins VR256:$src1, VR256:$src2, i256mem:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
|
[(set VR256:$dst,
|
|
(Int256 VR256:$src1, VR256:$src2,
|
|
(bitconvert (loadv4i64 addr:$src3))))]>,
|
|
XOP_4V, VEX_I8IMM, VEX_W, MemOp4, VEX_L;
|
|
def rmrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst),
|
|
(ins VR256:$src1, f256mem:$src2, VR256:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
|
[(set VR256:$dst,
|
|
(Int256 VR256:$src1, (bitconvert (loadv4i64 addr:$src2)),
|
|
VR256:$src3))]>,
|
|
XOP_4V, VEX_I8IMM, VEX_L;
|
|
// For disassembler
|
|
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
|
|
def rrrY_REV : IXOPi8<opc, MRMSrcReg, (outs VR256:$dst),
|
|
(ins VR256:$src1, VR256:$src2, VR256:$src3),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
|
|
[]>, XOP_4V, VEX_I8IMM, VEX_W, MemOp4, VEX_L;
|
|
}
|
|
|
|
let ExeDomain = SSEPackedInt in {
|
|
defm VPCMOV : xop4op_int<0xA2, "vpcmov",
|
|
int_x86_xop_vpcmov, int_x86_xop_vpcmov_256>;
|
|
}
|
|
|
|
let Predicates = [HasXOP] in {
|
|
def : Pat<(v2i64 (or (and VR128:$src3, VR128:$src1),
|
|
(X86andnp VR128:$src3, VR128:$src2))),
|
|
(VPCMOVrrr VR128:$src1, VR128:$src2, VR128:$src3)>;
|
|
|
|
def : Pat<(v4i64 (or (and VR256:$src3, VR256:$src1),
|
|
(X86andnp VR256:$src3, VR256:$src2))),
|
|
(VPCMOVrrrY VR256:$src1, VR256:$src2, VR256:$src3)>;
|
|
}
|
|
|
|
multiclass xop5op<bits<8> opc, string OpcodeStr, Intrinsic Int128,
|
|
Intrinsic Int256, PatFrag ld_128, PatFrag ld_256> {
|
|
def rr : IXOP5<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, VR128:$src3, u8imm:$src4),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
|
|
[(set VR128:$dst,
|
|
(Int128 VR128:$src1, VR128:$src2, VR128:$src3, imm:$src4))]>;
|
|
def rm : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, f128mem:$src3, u8imm:$src4),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
|
|
[(set VR128:$dst,
|
|
(Int128 VR128:$src1, VR128:$src2, (ld_128 addr:$src3), imm:$src4))]>,
|
|
VEX_W, MemOp4;
|
|
def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst),
|
|
(ins VR128:$src1, f128mem:$src2, VR128:$src3, u8imm:$src4),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
|
|
[(set VR128:$dst,
|
|
(Int128 VR128:$src1, (ld_128 addr:$src2), VR128:$src3, imm:$src4))]>;
|
|
// For disassembler
|
|
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
|
|
def rr_REV : IXOP5<opc, MRMSrcReg, (outs VR128:$dst),
|
|
(ins VR128:$src1, VR128:$src2, VR128:$src3, u8imm:$src4),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
|
|
[]>, VEX_W, MemOp4;
|
|
|
|
def rrY : IXOP5<opc, MRMSrcReg, (outs VR256:$dst),
|
|
(ins VR256:$src1, VR256:$src2, VR256:$src3, u8imm:$src4),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
|
|
[(set VR256:$dst,
|
|
(Int256 VR256:$src1, VR256:$src2, VR256:$src3, imm:$src4))]>, VEX_L;
|
|
def rmY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
|
|
(ins VR256:$src1, VR256:$src2, f256mem:$src3, u8imm:$src4),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
|
|
[(set VR256:$dst,
|
|
(Int256 VR256:$src1, VR256:$src2, (ld_256 addr:$src3), imm:$src4))]>,
|
|
VEX_W, MemOp4, VEX_L;
|
|
def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst),
|
|
(ins VR256:$src1, f256mem:$src2, VR256:$src3, u8imm:$src4),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
|
|
[(set VR256:$dst,
|
|
(Int256 VR256:$src1, (ld_256 addr:$src2), VR256:$src3, imm:$src4))]>,
|
|
VEX_L;
|
|
// For disassembler
|
|
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
|
|
def rrY_REV : IXOP5<opc, MRMSrcReg, (outs VR256:$dst),
|
|
(ins VR256:$src1, VR256:$src2, VR256:$src3, u8imm:$src4),
|
|
!strconcat(OpcodeStr,
|
|
"\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"),
|
|
[]>, VEX_W, MemOp4, VEX_L;
|
|
}
|
|
|
|
let ExeDomain = SSEPackedDouble in
|
|
defm VPERMIL2PD : xop5op<0x49, "vpermil2pd", int_x86_xop_vpermil2pd,
|
|
int_x86_xop_vpermil2pd_256, loadv2f64, loadv4f64>;
|
|
|
|
let ExeDomain = SSEPackedSingle in
|
|
defm VPERMIL2PS : xop5op<0x48, "vpermil2ps", int_x86_xop_vpermil2ps,
|
|
int_x86_xop_vpermil2ps_256, loadv4f32, loadv8f32>;
|
|
|