llvm-project/mlir/test/Transforms
Uday Bondhugula bc2a543225 fix loop unroll and jam - operand mapping - imperfect nest case
- fix operand mapping while cloning sub-blocks to jam - was incorrect
  for imperfect nests where def/use was across sub-blocks
- strengthen/generalize the first test case to cover the previously
  missed scenario
- clean up the other cases while on this.

Previously, unroll-jamming the following nest
```
    affine.for %arg0 = 0 to 2048 {
      %0 = alloc() : memref<512x10xf32>
      affine.for %arg1 = 0 to 10 {
        %1 = affine.load %0[%arg0, %arg1] : memref<512x10xf32>
      }
      dealloc %0 : memref<512x10xf32>
    }
```

would yield

```
      %0 = alloc() : memref<512x10xf32>
      %1 = affine.apply #map0(%arg0)
      %2 = alloc() : memref<512x10xf32>
      affine.for %arg1 = 0 to 10 {
        %4 = affine.load %0[%arg0, %arg1] : memref<512x10xf32>
        %5 = affine.apply #map0(%arg0)
        %6 = affine.load %0[%5, %arg1] : memref<512x10xf32>
      }
      dealloc %0 : memref<512x10xf32>
      %3 = affine.apply #map0(%arg0)
      dealloc %0 : memref<512x10xf32>

```

instead of

```

module {
    affine.for %arg0 = 0 to 2048 step 2 {
      %0 = alloc() : memref<512x10xf32>
      %1 = affine.apply #map0(%arg0)
      %2 = alloc() : memref<512x10xf32>
      affine.for %arg1 = 0 to 10 {
        %4 = affine.load %0[%arg0, %arg1] : memref<512x10xf32>
        %5 = affine.apply #map0(%arg0)
        %6 = affine.load %2[%5, %arg1] : memref<512x10xf32>
      }
      dealloc %0 : memref<512x10xf32>
      %3 = affine.apply #map0(%arg0)
      dealloc %2 : memref<512x10xf32>
    }
```

Signed-off-by: Uday Bondhugula <uday@polymagelabs.com>

Closes tensorflow/mlir#98

COPYBARA_INTEGRATE_REVIEW=https://github.com/tensorflow/mlir/pull/98 from bondhugula:ujam ddbc853f69b5608b3e8ff9b5ac1f6a5a0bb315a4
PiperOrigin-RevId: 266073460
2019-08-28 23:42:50 -07:00
..
Vectorize Use "standard" load and stores in LowerVectorTransfers 2019-07-26 02:34:24 -07:00
affine-data-copy.mlir Introduce explicit copying optimization by generalizing the DMA generation pass 2019-08-01 16:31:58 -07:00
canonicalize.mlir Standardize the value numbering in the AsmPrinter. 2019-07-09 10:41:00 -07:00
constant-fold.mlir Refactor ElementsAttr::getValue and DenseElementsAttr::getSplatValue. 2019-08-14 15:03:53 -07:00
cse.mlir Standardize the value numbering in the AsmPrinter. 2019-07-09 10:41:00 -07:00
dma-generate.mlir Introduce explicit copying optimization by generalizing the DMA generation pass 2019-08-01 16:31:58 -07:00
loop-coalescing.mlir Introduce loop coalescing utility and a simple pass 2019-07-16 13:43:44 -07:00
loop-fusion-dependence-check.mlir Globally change load/store/dma_start/dma_wait operations over to affine.load/store/dma_start/dma_wait. 2019-07-03 14:37:06 -07:00
loop-fusion-slice-computation.mlir Globally change load/store/dma_start/dma_wait operations over to affine.load/store/dma_start/dma_wait. 2019-07-03 14:37:06 -07:00
loop-fusion.mlir Affine loop parallelism detection: conservatively handle unknown ops 2019-07-23 10:18:46 -07:00
loop-invariant-code-motion.mlir Standardize the value numbering in the AsmPrinter. 2019-07-09 10:41:00 -07:00
loop-tiling.mlir Standardize the value numbering in the AsmPrinter. 2019-07-09 10:41:00 -07:00
lower-affine.mlir Lower affine control flow to std control flow to LLVM dialect 2019-07-12 08:44:28 -07:00
memref-bound-check.mlir Standardize the value numbering in the AsmPrinter. 2019-07-09 10:41:00 -07:00
memref-dataflow-opt.mlir Standardize the value numbering in the AsmPrinter. 2019-07-09 10:41:00 -07:00
memref-dependence-check.mlir Globally change load/store/dma_start/dma_wait operations over to affine.load/store/dma_start/dma_wait. 2019-07-03 14:37:06 -07:00
parallelism-detection.mlir Affine loop parallelism detection: conservatively handle unknown ops 2019-07-23 10:18:46 -07:00
parametric-mapping.mlir Utility function to map a loop on a parametric grid of virtual processors 2019-07-19 11:40:31 -07:00
parametric-tiling.mlir Refactor LoopParametricTiling as a test pass - NFC 2019-07-22 04:31:17 -07:00
pipeline-data-transfer.mlir Refactor / improve replaceAllMemRefUsesWith 2019-08-27 17:56:56 -07:00
simplify-affine-structures.mlir Standardize the value numbering in the AsmPrinter. 2019-07-09 10:41:00 -07:00
slicing-utils.mlir Fix backward slice corner case 2019-07-26 03:49:17 -07:00
strip-debuginfo.mlir Replace the implementation of Function and Module with FuncOp and ModuleOp. 2019-07-03 14:37:18 -07:00
test-canonicalize.mlir Support folding of ops with inner ops in GreedyPatternRewriteDriver. 2019-08-26 09:44:39 -07:00
test-legalizer-analysis.mlir Add support for an analysis mode to DialectConversion. 2019-07-25 11:31:07 -07:00
test-legalizer.mlir Allow isolated regions to form isolated SSA name scopes in the printer. 2019-08-19 15:27:10 -07:00
unroll-jam.mlir fix loop unroll and jam - operand mapping - imperfect nest case 2019-08-28 23:42:50 -07:00
unroll.mlir Standardize the value numbering in the AsmPrinter. 2019-07-09 10:41:00 -07:00