llvm-project/mlir/test
Uday Bondhugula bc2a543225 fix loop unroll and jam - operand mapping - imperfect nest case
- fix operand mapping while cloning sub-blocks to jam - was incorrect
  for imperfect nests where def/use was across sub-blocks
- strengthen/generalize the first test case to cover the previously
  missed scenario
- clean up the other cases while on this.

Previously, unroll-jamming the following nest
```
    affine.for %arg0 = 0 to 2048 {
      %0 = alloc() : memref<512x10xf32>
      affine.for %arg1 = 0 to 10 {
        %1 = affine.load %0[%arg0, %arg1] : memref<512x10xf32>
      }
      dealloc %0 : memref<512x10xf32>
    }
```

would yield

```
      %0 = alloc() : memref<512x10xf32>
      %1 = affine.apply #map0(%arg0)
      %2 = alloc() : memref<512x10xf32>
      affine.for %arg1 = 0 to 10 {
        %4 = affine.load %0[%arg0, %arg1] : memref<512x10xf32>
        %5 = affine.apply #map0(%arg0)
        %6 = affine.load %0[%5, %arg1] : memref<512x10xf32>
      }
      dealloc %0 : memref<512x10xf32>
      %3 = affine.apply #map0(%arg0)
      dealloc %0 : memref<512x10xf32>

```

instead of

```

module {
    affine.for %arg0 = 0 to 2048 step 2 {
      %0 = alloc() : memref<512x10xf32>
      %1 = affine.apply #map0(%arg0)
      %2 = alloc() : memref<512x10xf32>
      affine.for %arg1 = 0 to 10 {
        %4 = affine.load %0[%arg0, %arg1] : memref<512x10xf32>
        %5 = affine.apply #map0(%arg0)
        %6 = affine.load %2[%5, %arg1] : memref<512x10xf32>
      }
      dealloc %0 : memref<512x10xf32>
      %3 = affine.apply #map0(%arg0)
      dealloc %2 : memref<512x10xf32>
    }
```

Signed-off-by: Uday Bondhugula <uday@polymagelabs.com>

Closes tensorflow/mlir#98

COPYBARA_INTEGRATE_REVIEW=https://github.com/tensorflow/mlir/pull/98 from bondhugula:ujam ddbc853f69b5608b3e8ff9b5ac1f6a5a0bb315a4
PiperOrigin-RevId: 266073460
2019-08-28 23:42:50 -07:00
..
AffineOps Fix verification of zero-dim memref in affine.load/affine.store/std.load/std.store 2019-08-07 10:31:49 -07:00
Conversion Enhance GPU To SPIR-V conversion to support builtins and load/store ops. 2019-08-27 10:50:23 -07:00
Dialect Add verification for dimension attribute on GPUDialect index operations. 2019-08-28 23:39:57 -07:00
EDSC NFC: Move AffineOps dialect to the Dialect sub-directory. 2019-08-20 15:36:39 -07:00
Examples Update Ch.2 of the Toy tutorial. 2019-08-27 12:44:27 -07:00
IR Tweak to the pretty type parser to recognize that `->` is a special token. 2019-08-28 13:55:42 -07:00
LLVMIR Add 3 additional intrinsic ops to NVVM dialect, in preparation to implement block-wide reduce. 2019-08-27 10:56:18 -07:00
Linalg Lower linalg.copy to LLVM dialect in the presence of transposes. 2019-08-23 17:45:19 -07:00
Pass Enable multi-threading in the pass manager by default. 2019-05-06 08:17:58 -07:00
Quantizer Change the attribute dictionary syntax to separate name and value with '='. 2019-06-25 19:06:34 -07:00
SDBM NFC: Move LLVMIR, SDBM, and StandardOps to the Dialect/ directory. 2019-08-19 11:01:25 -07:00
Target Add 3 additional intrinsic ops to NVVM dialect, in preparation to implement block-wide reduce. 2019-08-27 10:56:18 -07:00
Transforms fix loop unroll and jam - operand mapping - imperfect nest case 2019-08-28 23:42:50 -07:00
Unit Add build files and update README. 2019-03-30 11:23:22 -07:00
lib Add implementation for tensor_load and tensor_store operations. 2019-08-28 11:25:52 -07:00
mlir-cpu-runner Add lowering of linalg.copy to an external C++ library and a test. 2019-08-23 11:09:53 -07:00
mlir-cuda-runner JitRunner: support entry functions returning void 2019-08-20 07:46:17 -07:00
mlir-tblgen Add I32ElementsAttr to OpBase 2019-08-22 19:05:40 -07:00
APITest.h Use FileCheck to test SDBM 2019-05-20 13:48:53 -07:00
CMakeLists.txt Move Linalg and VectorOps dialects to the Dialect subdir - NFC 2019-08-19 17:11:38 -07:00
lit.cfg.py Add an mlir-cuda-runner tool. 2019-07-04 07:53:54 -07:00
lit.site.cfg.py.in Move Linalg and VectorOps dialects to the Dialect subdir - NFC 2019-08-19 17:11:38 -07:00