| .. |
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GlobalISel
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
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2019-08-20 22:53:24 +00:00 |
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intrinsics
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[RISCV] Lower llvm.trap and llvm.debugtrap
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2019-10-28 09:54:33 +00:00 |
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add-before-shl.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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add-imm.ll
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[RISCV] optimize addition with a pair of (addi imm)
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2020-07-07 18:57:28 -07:00 |
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addc-adde-sube-subc.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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addcarry.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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addimm-mulimm.ll
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[RISCV][test] Add a test for (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) transformation
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2020-07-10 18:33:12 -07:00 |
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align.ll
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…
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alloca.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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alu8.ll
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…
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alu16.ll
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…
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alu32.ll
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[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
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2019-08-06 00:24:00 +00:00 |
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alu64.ll
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[RISCV] Add isel pattern to match (i64 (sra (shl X, 32), C)) to SRAIW if C > 32.
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2020-11-25 21:57:48 -08:00 |
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analyze-branch.ll
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…
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arith-with-overflow.ll
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[TargetLowering] Simplify expansion of S{ADD,SUB}O
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2019-09-30 07:58:50 +00:00 |
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atomic-cmpxchg-flag.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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atomic-cmpxchg.ll
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[LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG
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2020-04-01 15:51:26 +01:00 |
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atomic-fence.ll
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…
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atomic-load-store.ll
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…
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atomic-rmw.ll
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[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move
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2020-08-27 10:32:22 +01:00 |
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attributes.ll
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[RISCV] ELF attribute section for RISC-V.
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2020-03-31 16:16:19 +08:00 |
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bare-select.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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blockaddress.ll
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[RISCV] Fix inaccurate annotations on PseudoBRIND
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2020-08-21 11:38:42 +01:00 |
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branch-relaxation.ll
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[RISCV] Indirect branch generation in position independent code
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2020-08-17 13:09:26 +01:00 |
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branch.ll
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Revert "[BPI] Improve static heuristics for integer comparisons"
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2020-08-17 20:44:33 +02:00 |
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bswap-ctlz-cttz-ctpop.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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byval.ll
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OpaquePtr: Bulk update tests to use typed byval
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2020-11-20 14:00:46 -05:00 |
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callee-saved-fpr32s.ll
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[RISCV] Fold ADDIs into load/stores with nonzero offsets
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2020-07-06 17:32:57 +01:00 |
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callee-saved-fpr64s.ll
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[RISCV] Fold ADDIs into load/stores with nonzero offsets
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2020-07-06 17:32:57 +01:00 |
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callee-saved-gprs.ll
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[RISCV] Fold ADDIs into load/stores with nonzero offsets
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2020-07-06 17:32:57 +01:00 |
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calling-conv-ilp32-ilp32f-common.ll
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[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move
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2020-08-27 10:32:22 +01:00 |
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calling-conv-ilp32-ilp32f-ilp32d-common.ll
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OpaquePtr: Bulk update tests to use typed sret
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2020-11-20 17:58:26 -05:00 |
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calling-conv-ilp32.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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calling-conv-ilp32d.ll
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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calling-conv-ilp32f-ilp32d-common.ll
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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calling-conv-lp64-lp64f-common.ll
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…
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calling-conv-lp64-lp64f-lp64d-common.ll
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OpaquePtr: Bulk update tests to use typed sret
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2020-11-20 17:58:26 -05:00 |
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calling-conv-lp64.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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calling-conv-rv32f-ilp32.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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calling-conv-sext-zext.ll
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…
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calls.ll
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[RISCV] Lower calls through PLT
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2019-06-18 14:29:45 +00:00 |
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cmp-bool.ll
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[DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1)
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2020-07-15 07:34:22 +00:00 |
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codemodel-lowering.ll
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[RISCV] Fix inaccurate annotations on PseudoBRIND
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2020-08-21 11:38:42 +01:00 |
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compress-float.ll
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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compress-inline-asm.ll
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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compress.ll
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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copy-frameindex.mir
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[RISCV] Only return DestSourcePair from isCopyInstrImpl for registers
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2020-11-03 03:55:47 +00:00 |
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copysign-casts.ll
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[LegalizeTypes][RISCV] Soften FCOPYSIGN operand
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2019-11-26 15:22:55 +00:00 |
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disable-tail-calls.ll
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…
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disjoint.ll
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[RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hook
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2019-11-05 09:39:06 +00:00 |
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div.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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double-arith.ll
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[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
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2020-11-25 15:07:34 -08:00 |
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double-bitmanip-dagcombines.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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double-br-fcmp.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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double-calling-conv.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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double-convert.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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double-fcmp.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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double-frem.ll
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…
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double-imm.ll
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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double-intrinsics.ll
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[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
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2020-11-25 15:07:34 -08:00 |
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double-isnan.ll
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[RISCV] Add patterns for checking isnan
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2020-05-02 15:01:04 +01:00 |
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double-mem.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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double-previous-failure.ll
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[RISCV] Implement Hooks to avoid chaining SELECT
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2020-07-01 11:56:31 +01:00 |
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double-select-fcmp.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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double-stack-spill-restore.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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dwarf-eh.ll
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[RISCV][NFC] Remove outdated TODO from test/CodeGen/RISCV/dwarf-eh.ll
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2019-07-17 14:04:48 +00:00 |
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exception-pointer-register.ll
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[RISCV] Fix wrong CFI directives
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2019-11-14 18:29:50 +00:00 |
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fastcc-float.ll
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[RISCV] Support fast calling convention
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2019-10-15 02:04:29 +00:00 |
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fastcc-int.ll
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[RISCV] Support fast calling convention
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2019-10-15 02:04:29 +00:00 |
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fixups-diff.ll
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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fixups-relax-diff.ll
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[llvm-readobj] Update tests because of changes in llvm-readobj behavior
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2020-07-20 10:39:04 +01:00 |
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float-arith.ll
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[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
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2020-11-25 15:07:34 -08:00 |
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float-bit-preserving-dagcombines.ll
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…
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float-bitmanip-dagcombines.ll
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…
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float-br-fcmp.ll
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[RISCV] Select +0.0 immediate using fmv.{w,d}.x / fcvt.d.w
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2020-03-20 09:42:24 +00:00 |
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float-convert.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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float-fcmp.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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float-frem.ll
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…
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float-imm.ll
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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float-intrinsics.ll
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[RISCV] Add an implementation of isFMAFasterThanFMulAndFAdd
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2020-11-25 15:07:34 -08:00 |
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float-isnan.ll
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[RISCV] Add patterns for checking isnan
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2020-05-02 15:01:04 +01:00 |
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float-mem.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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float-select-fcmp.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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flt-rounds.ll
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…
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fold-addi-loadstore.ll
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[RISCV] Fold ADDIs into load/stores with nonzero offsets
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2020-07-06 17:32:57 +01:00 |
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fp-imm.ll
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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fp16-promote.ll
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[RISCV] Add support for half-precision floats
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2019-10-25 14:02:02 +01:00 |
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fp128.ll
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[RISCV] Fold ADDIs into load/stores with nonzero offsets
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2020-07-06 17:32:57 +01:00 |
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frame-info.ll
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[RISCV][NFC] Fix use of missing attribute groups in tests
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2019-12-23 15:39:04 +00:00 |
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frame.ll
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[RISCV][NFC] Fix use of missing attribute groups in tests
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2019-12-23 15:39:04 +00:00 |
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frameaddr-returnaddr.ll
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…
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get-register-invalid.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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get-register-noreserve.ll
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[RISCV] Implement the TargetLowering::getRegisterByName hook
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2019-11-04 11:23:54 +00:00 |
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get-register-reserve.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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get-setcc-result-type.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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ghccc-rv32.ll
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[RISCV] Add GHC calling convention
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2020-11-24 22:35:23 +00:00 |
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ghccc-rv64.ll
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[RISCV] Add GHC calling convention
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2020-11-24 22:35:23 +00:00 |
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hoist-global-addr-base.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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i32-icmp.ll
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[RISCV] Optimize seteq/setne pattern expansions for better code size
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2020-02-11 22:45:15 +08:00 |
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imm-cse.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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imm.ll
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[RISCV][NFC] Add more tests for 32-bit constant materialization
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2020-10-22 11:36:34 +01:00 |
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indirectbr.ll
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[RISCV] Fix inaccurate annotations on PseudoBRIND
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2020-08-21 11:38:42 +01:00 |
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init-array.ll
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…
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inline-asm-abi-names.ll
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[MC][RISCV] Set UseIntegratedAssembler to true
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2020-07-12 21:04:48 -07:00 |
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inline-asm-clobbers.ll
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[RISCV] Add support for lowering floating point inlineasm clobbers
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2019-07-31 09:07:21 +00:00 |
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inline-asm-d-abi-names.ll
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[RISCV] Allow ABI Names in Inline Assembly Constraints
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2019-08-08 14:59:16 +00:00 |
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inline-asm-d-constraint-f.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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inline-asm-f-abi-names.ll
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[RISCV] Allow ABI Names in Inline Assembly Constraints
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2019-08-08 14:59:16 +00:00 |
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inline-asm-f-constraint-f.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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inline-asm-i-constraint-i1.ll
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…
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inline-asm-invalid.ll
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Emit diagnostic if an inline asm constraint requires an immediate
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2019-08-03 05:52:47 +00:00 |
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inline-asm.ll
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[MC][RISCV] Set UseIntegratedAssembler to true
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2020-07-12 21:04:48 -07:00 |
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interrupt-attr-args-error.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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interrupt-attr-callee.ll
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[RISCV] Correct the CallPreservedMask for the function call in an interrupt handler
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2020-02-15 09:14:04 +08:00 |
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interrupt-attr-invalid.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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interrupt-attr-nocall.ll
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[RISCV] Fold ADDIs into load/stores with nonzero offsets
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2020-07-06 17:32:57 +01:00 |
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interrupt-attr-ret-error.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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interrupt-attr.ll
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Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351
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2019-12-24 15:57:33 -08:00 |
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jumptable.ll
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…
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large-stack.ll
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[MC][RISCV] Set UseIntegratedAssembler to true
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2020-07-12 21:04:48 -07:00 |
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legalize-fneg.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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lit.local.cfg
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…
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lsr-legaladdimm.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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machineoutliner.mir
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[RISCV] Enable the machine outliner for RISC-V
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2019-12-19 16:41:53 +00:00 |
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mattr-invalid-combination.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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mem.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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mem64.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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mir-target-flags.ll
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Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
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2020-07-14 11:15:01 +01:00 |
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module-target-abi.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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module-target-abi2.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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mul.ll
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[RISCV] Optimize multiplication by constant
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2020-07-07 18:50:24 -07:00 |
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musttail-call.ll
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OpaquePtr: Bulk update tests to use typed sret
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2020-11-20 17:58:26 -05:00 |
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neg-abs.ll
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[SelectionDAGBuilder] Add SPF_NABS support to visitSelect
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2020-11-25 14:54:26 -08:00 |
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nomerge.ll
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Add NoMerge MIFlag to avoid MIR branch folding
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2020-05-29 12:31:06 -07:00 |
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option-nopic.ll
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[RISCV][AsmParser] Implement .option (no)pic
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2020-04-17 12:08:30 +00:00 |
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option-norelax.ll
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[llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:`
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2020-03-05 18:05:28 -08:00 |
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option-norvc.ll
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
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2020-03-15 17:46:23 -07:00 |
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option-pic.ll
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[RISCV][AsmParser] Implement .option (no)pic
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2020-04-17 12:08:30 +00:00 |
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option-relax.ll
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[llvm-objdump] -d: print `00000000 <foo>:` instead of `00000000 foo:`
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2020-03-05 18:05:28 -08:00 |
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option-rvc.ll
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[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options
|
2020-03-15 17:46:23 -07:00 |
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pic-models.ll
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Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
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2020-07-14 11:15:01 +01:00 |
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pr40333.ll
|
…
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prefetch.ll
|
…
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readcyclecounter.ll
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[RISCV] Support @llvm.readcyclecounter() Intrinsic
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2019-07-05 12:35:21 +00:00 |
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rem.ll
|
…
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remat.ll
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[RISCV][NFC] Fix use of missing attribute groups in tests
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2019-12-23 15:39:04 +00:00 |
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reserved-reg-errors.ll
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[RISCV] Add support for -ffixed-xX flags
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2019-10-22 21:25:01 +01:00 |
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reserved-regs.ll
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[RISCV] Add support for -ffixed-xX flags
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2019-10-22 21:25:01 +01:00 |
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rotl-rotr.ll
|
…
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rv32Zbb.ll
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[RISCV] Add test cases to check that we use (smax X, (neg X)) for abs with Zbb extension.
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2020-11-25 12:48:43 -08:00 |
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rv32Zbbp.ll
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[RISCV] Add isel patterns for using PACK for zext.h and zext.w.
|
2020-11-09 10:13:45 -08:00 |
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rv32Zbp.ll
|
[RISCV] Combine (GORCI (GORCI x, C2), C1) -> (GORCI x, C1|C2).
|
2020-11-30 08:42:46 -08:00 |
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rv32Zbs.ll
|
[RISCV] Add isel patterns to use SBSET for (1 << X) by using X0 as the input.
|
2020-11-26 15:35:13 -08:00 |
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rv32Zbt.ll
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[RISCV] Add an ANDI to shift amount of FSL/FSR instructions
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2020-11-12 07:33:40 -08:00 |
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rv32e.ll
|
Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
|
2020-02-13 10:16:06 -08:00 |
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rv32i-rv64i-float-double.ll
|
[RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCall
|
2019-08-28 23:40:37 +00:00 |
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rv64-large-stack.ll
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[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore
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2019-10-04 02:00:57 +00:00 |
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rv64Zbb.ll
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[RISCV][LegalizeTypes] Teach type legalizer that it can promote UMIN/UMAX using SExtPromotedInteger if that's better for the target.
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2020-11-27 11:37:25 -08:00 |
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rv64Zbbp.ll
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[RISCV] Add RISCVISD::ROLW/RORW use those for custom legalizing i32 rotl/rotr on RV64IZbb.
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2020-11-20 10:25:47 -08:00 |
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rv64Zbp.ll
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[RISCV] Combine (GORCI (GORCI x, C2), C1) -> (GORCI x, C1|C2).
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2020-11-30 08:42:46 -08:00 |
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rv64Zbs.ll
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[RISCV] Add isel patterns to use SBSET for (1 << X) by using X0 as the input.
|
2020-11-26 15:35:13 -08:00 |
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rv64Zbt.ll
|
[RISCV] Custom type legalize i32 fshl/fshr on RV64 with Zbt.
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2020-11-25 10:01:47 -08:00 |
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rv64d-double-convert.ll
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…
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rv64f-float-convert.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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rv64i-complex-float.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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rv64i-demanded-bits.ll
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[RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW
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2020-10-29 14:52:53 -07:00 |
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rv64i-double-softfloat.ll
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[RISCV] Use the 'si' lib call for (double (fp_to_sint/uint i32 X)) when F extension is enabled.
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2020-11-05 10:46:45 -08:00 |
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rv64i-exhaustive-w-insts.ll
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[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
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2019-08-06 00:24:00 +00:00 |
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rv64i-single-softfloat.ll
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Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC""
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2020-11-04 19:58:11 -08:00 |
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rv64i-tricky-shifts.ll
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…
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rv64i-w-insts-legalization.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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rv64m-exhaustive-w-insts.ll
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[RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions
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2019-08-06 00:24:00 +00:00 |
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rv64m-w-insts-legalization.ll
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Revert "[BPI] Improve static heuristics for integer comparisons"
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2020-08-17 20:44:33 +02:00 |
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saverestore.ll
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[RISCV] Add support for save/restore of callee-saved registers via libcalls
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2020-02-11 21:23:03 +00:00 |
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sdata-limit-0.ll
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…
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sdata-limit-4.ll
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…
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sdata-limit-8.ll
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…
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sdata-local-sym.ll
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…
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select-and.ll
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[RISCV] Implement Hooks to avoid chaining SELECT
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2020-07-01 11:56:31 +01:00 |
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select-cc.ll
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…
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select-const.ll
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[RISCV] Support Constant Pools in Load/Store Peephole
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2020-05-11 19:20:38 +01:00 |
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select-optimize-multiple.ll
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[RISCV] Add MemOperand to the instruction created by storeRegToStackSlot/loadRegFromStackSlot
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2020-11-18 19:20:03 -08:00 |
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select-optimize-multiple.mir
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[MachineVerifier] Verify that a DBG_VALUE has a debug location
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2020-05-28 13:53:40 -07:00 |
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select-or.ll
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[RISCV] Implement Hooks to avoid chaining SELECT
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2020-07-01 11:56:31 +01:00 |
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setcc-logic.ll
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[RISCV] Optimize seteq/setne pattern expansions for better code size
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2020-02-11 22:45:15 +08:00 |
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sext-zext-trunc.ll
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[DAGCombiner] Precommit Sext Tests for D91589
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2020-11-18 15:56:16 +00:00 |
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shadowcallstack.ll
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[RISCV] Support Shadow Call Stack
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2020-09-17 16:02:35 -07:00 |
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shift-masked-shamt.ll
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…
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shifts.ll
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Reland [MachineCopyPropagation] Extend MCP to do trivial copy backward propagation.
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2019-12-05 14:32:11 +08:00 |
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shrinkwrap.ll
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[RISCV] Add support for save/restore of callee-saved registers via libcalls
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2020-02-11 21:23:03 +00:00 |
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split-offsets.ll
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[RISCV] Fix wrong CFI directives
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2019-11-14 18:29:50 +00:00 |
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split-sp-adjust.ll
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[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore
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2019-10-04 02:00:57 +00:00 |
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srem-lkk.ll
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[RISCV][NFC] Add nounwind to LKK test functions
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2019-11-11 09:51:37 +00:00 |
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srem-vector-lkk.ll
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[RISCV] srem-vector-lkk.ll - remove unused check prefix
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2020-11-11 18:38:23 +00:00 |
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stack-realignment-with-variable-sized-objects.ll
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[RISCV] Handle variable sized objects with the stack need to be realigned
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2019-11-16 12:39:53 +08:00 |
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stack-realignment.ll
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[RISCV] Split SP adjustment to reduce the offset of callee saved register spill and restore
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2019-10-04 02:00:57 +00:00 |
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stack-store-check.ll
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[RISCV] Fix isStoreToStackSlot
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2020-07-14 12:36:42 +00:00 |
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subtarget-features-std-ext.ll
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[RISCV] Support ABI checking with per function target-features
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2020-01-22 08:12:28 -08:00 |
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tail-calls.ll
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OpaquePtr: Bulk update tests to use typed sret
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2020-11-20 17:58:26 -05:00 |
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target-abi-invalid.ll
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…
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target-abi-valid.ll
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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thread-pointer.ll
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[RISCV] Support llvm.thread.pointer
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2020-03-27 17:30:12 -07:00 |
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tls-models.ll
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Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo"
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2020-07-14 11:15:01 +01:00 |
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umulo-128-legalisation-lowering.ll
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[RISCV] Switch to the Machine Scheduler
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2019-09-17 11:15:35 +00:00 |
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urem-lkk.ll
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[RISCV][NFC] Add nounwind to LKK test functions
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2019-11-11 09:51:37 +00:00 |
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urem-vector-lkk.ll
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[RISCV][NFC] Add nounwind to LKK test functions
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2019-11-11 09:51:37 +00:00 |
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vararg.ll
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[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move
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2020-08-27 10:32:22 +01:00 |
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verify-instr.mir
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Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""
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2020-02-13 10:16:06 -08:00 |
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wide-mem.ll
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[RISCV] Fold ADDIs into load/stores with nonzero offsets
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2020-07-06 17:32:57 +01:00 |
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zext-with-load-is-free.ll
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[RISCV] Implement Hooks to avoid chaining SELECT
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2020-07-01 11:56:31 +01:00 |
bfc4f29f46