llvm-project/llvm/lib/Transforms/InstCombine
Roman Lebedev 7cdeac43e5 [InstCombine] Fold conditional sign-extend of high-bit-extract into high-bit-extract-with-signext (PR42389)
This can come up in Bit Stream abstractions.

The pattern looks big/scary, but it can't be simplified any further.
It only is so simple because a number of my preparatory folds had
happened already (shift amount reassociation / shift amount
reassociation in bit test, sign bit test detection).

Highlights:
* There are two main flavors: https://rise4fun.com/Alive/zWi
  The difference is add vs. sub, and left-shift of -1 vs. 1
* Since we only change the shift opcode,
  we can preserve the exact-ness: https://rise4fun.com/Alive/4u4
* There can be truncation after high-bit-extraction:
  https://rise4fun.com/Alive/slHc1   (the main pattern i'm after!)
  Which means that we need to ignore zext of shift amounts and of NBits.
* The sign-extending magic can be extended itself (in add pattern
  via sext, in sub pattern via zext. not the other way around!)
  https://rise4fun.com/Alive/NhG
  (or those sext/zext can be sinked into `select`!)
  Which again means we should pay attention when matching NBits.
* We can have both truncation of extraction and widening of magic:
  https://rise4fun.com/Alive/XTw
  In other words, i don't believe we need to have any checks on
  bitwidths of any of these constructs.

This is worsened in general by the fact that we may have `sext` instead
of `zext` for shift amounts, and we don't yet canonicalize to `zext`,
although we should. I have not done anything about that here.

Also, we really should have something to weed out `sub` like these,
by folding them into `add` variant.

https://bugs.llvm.org/show_bug.cgi?id=42389

llvm-svn: 373964
2019-10-07 20:53:27 +00:00
..
CMakeLists.txt [InstCombine] Optimize `atomicrmw <op>, 0` into `load atomic` when possible 2019-02-07 21:27:23 +00:00
InstCombineAddSub.cpp [InstCombine] Fold conditional sign-extend of high-bit-extract into high-bit-extract-with-signext (PR42389) 2019-10-07 20:53:27 +00:00
InstCombineAndOrXor.cpp [InstCombine] foldUnsignedUnderflowCheck(): one last pattern with 'sub' (PR43251) 2019-09-25 22:59:59 +00:00
InstCombineAtomicRMW.cpp [Alignment][NFC] Remove StoreInst::setAlignment(unsigned) 2019-10-03 13:17:21 +00:00
InstCombineCalls.cpp [Alignment][NFC] Remove StoreInst::setAlignment(unsigned) 2019-10-03 13:17:21 +00:00
InstCombineCasts.cpp [InstCombine] don't assume 'inbounds' for bitcast pointer to GEP transform (PR43501) 2019-10-06 13:08:08 +00:00
InstCombineCompares.cpp [InstCombine] Move isSignBitCheck(), handle rest of the predicates 2019-10-07 20:53:08 +00:00
InstCombineInternal.h [InstCombine] Move isSignBitCheck(), handle rest of the predicates 2019-10-07 20:53:08 +00:00
InstCombineLoadStoreAlloca.cpp [Alignment][NFC] Remove StoreInst::setAlignment(unsigned) 2019-10-03 13:17:21 +00:00
InstCombineMulDivRem.cpp [InstCombine] fold fneg disguised as select+fmul (PR43497) 2019-10-06 14:15:48 +00:00
InstCombinePHI.cpp [InstCombine] SliceUpIllegalIntegerPHI - bail on out of range shifts 2019-06-24 13:13:36 +00:00
InstCombineSelect.cpp [InstCombine] allow icmp+binop folds before min/max bailout (PR43310) 2019-09-22 14:31:53 +00:00
InstCombineShifts.cpp [InstCombine][NFC] dropRedundantMaskingOfLeftShiftInput(): change how we deal with mask 2019-10-07 20:53:00 +00:00
InstCombineSimplifyDemanded.cpp [InstCombine][AMDGPU] Simplify tbuffer loads 2019-08-30 14:20:04 +00:00
InstCombineTables.td InstCombine/AMDGPU: Add dimension-aware image intrinsics to SimplifyDemanded 2018-06-21 13:37:31 +00:00
InstCombineVectorOps.cpp [InstCombine] fold extract+insert into identity shuffle 2019-09-08 19:03:01 +00:00
InstructionCombining.cpp [InstCombine] Use m_Zero instead of isNullValue() when checking if a GEP index is all zeroes to prevent an infinite loop. 2019-09-26 17:20:50 +00:00
LLVMBuild.txt Update the file headers across all of the LLVM projects in the monorepo 2019-01-19 08:50:56 +00:00