Craig Topper f225367305 [RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls. ... These allow getting a whole register from a larger lmul. Or inserting a whole register into a larger lmul register. Fractional lmuls are not supported as they would require a vslide. Based on this update to the intrinsic doc https://github.com/riscv/rvv-intrinsic-doc/pull/99 Reviewed By: HsiangKai Differential Revision: https://reviews.llvm.org/D104822		2021-06-24 18:06:36 -07:00
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rvb-intrinsics	[RISCV] [1/2] Add IR intrinsic for Zbe extension	2021-04-25 19:14:34 -07:00
rvv-intrinsics	[RISCV] Add vget/vset intrinsics for inserting and extracting between different lmuls.	2021-06-24 18:06:36 -07:00
rvv-intrinsics-overloaded	[RISCV] Reorder masked builtin operands. Use clang_builtin_alias for all overloaded vector builtins.	2021-05-02 10:57:25 -07:00
riscv-atomics.c	NFC: update clang tests to check ordering and alignment for atomicrmw/cmpxchg.	2021-02-11 17:35:09 -05:00
riscv-attr-builtin-alias-err.c	[Clang] Add clang attribute `clang_builtin_alias`.	2021-04-25 08:49:19 +08:00
riscv-attr-builtin-alias.c	[Clang] Add clang attribute `clang_builtin_alias`.	2021-04-25 08:49:19 +08:00
riscv-inline-asm-rvv.c	[RISCV] Add inline asm constraint 'vr' and 'vm' in Clang for RISC-V 'V'.	2021-03-30 09:47:27 +08:00
riscv-inline-asm.c	…
riscv-metadata.c	…
riscv-sdata-module-flag.c	…
riscv-v-debuginfo.c	[Clang][RISCV] Define RISC-V V builtin types	2021-02-18 10:17:31 +08:00
riscv-v-lifetime.cpp	[Clang][CodeGen] Set the size of llvm.lifetime to unknown for scalable types.	2021-06-07 23:30:13 +08:00
riscv32-ilp32-abi.c	…
riscv32-ilp32-ilp32f-abi.c	…
riscv32-ilp32-ilp32f-ilp32d-abi.c	…
riscv32-ilp32d-abi.c	…
riscv32-ilp32f-abi.c	…
riscv32-ilp32f-ilp32d-abi.c	…
riscv64-lp64-abi.c	…
riscv64-lp64-lp64f-abi.c	…
riscv64-lp64-lp64f-lp64d-abi.c	…
riscv64-lp64d-abi.c	…
riscv64-lp64f-lp64d-abi.c	…
rvv_errors.c	[RISCV] Validate the SEW and LMUL operands to __builtin_rvv_vsetvli(max)	2021-05-10 12:11:13 -07:00