forked from OSchip/llvm-project
25 lines
634 B
TableGen
25 lines
634 B
TableGen
// RUN: llvm-tblgen -gen-register-info -I %p/../../include -I %p/Common %s | FileCheck %s
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include "reg-with-subregs-common.td"
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// CHECK-LABEL: static const RegClassWeight RCWeightTable[] = {
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// CHECK: {1, 256}, // GPR32
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// CHECK: {2, 256}, // GPR_64
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// CHECK: {0, 256}, // GPR_64_W0
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def GPR_64_W0 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
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let Weight = 0;
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}
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// CHECK: {1, 256}, // GPR_64_W1
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def GPR_64_W1 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
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let Weight = 1;
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}
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// CHECK: {8, 256}, // GPR_64_W8
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def GPR_64_W8 : RegisterClass<"", [v2i32], 64, (add GPR64)> {
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let Weight = 8;
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}
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// CHECK: {32, 256}, // GPR_1024
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