forked from OSchip/llvm-project
23 lines
664 B
TableGen
23 lines
664 B
TableGen
// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def TestTargetInstrInfo : InstrInfo;
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def TestTarget : Target {
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let InstructionSet = TestTargetInstrInfo;
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}
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def REG : Register<"REG">;
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def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>;
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// CHECK-LABEL: OPC_CheckOpcode, TARGET_VAL(ISD::UDIVREM)
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// CHECK: OPC_EmitNode2, TARGET_VAL(::INSTR)
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// CHECK: Results = #2 #3
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// CHECK: OPC_CompleteMatch, 2, 3, 2
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def INSTR : Instruction {
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let OutOperandList = (outs GPR:$r1, GPR:$r0);
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let InOperandList = (ins GPR:$t0, GPR:$t1);
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let Pattern = [(set i32:$r0, i32:$r1, (udivrem i32:$t0, i32:$t1))];
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}
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