forked from OSchip/llvm-project
36 lines
957 B
TableGen
36 lines
957 B
TableGen
// RUN: llvm-tblgen %s | FileCheck %s
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// XFAIL: vg_leak
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// CHECK: --- Defs ---
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// CHECK: def A0 {
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// CHECK: bits<8> add = { 0, 0, 0, 1, 1, 0, 0, 0 };
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// CHECK: bits<8> sub = { 0, 0, 0, 1, 0, 0, 1, 0 };
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// CHECK: bits<8> and = { 0, 0, 0, 0, 0, 0, 0, 1 };
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// CHECK: bits<8> or = { 0, 0, 0, 1, 0, 1, 1, 1 };
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// CHECK: bits<8> xor = { 0, 0, 0, 1, 0, 1, 1, 0 };
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// CHECK: bits<8> srl = { 0, 0, 0, 0, 0, 0, 1, 0 };
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// CHECK: bits<8> sra = { 0, 0, 0, 0, 0, 0, 1, 0 };
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// CHECK: bits<8> shl = { 1, 0, 1, 0, 1, 0, 0, 0 };
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// CHECK: bits<8> sra = { 1, 1, 1, 1, 1, 1, 1, 1 };
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class A<bits<8> a, bits<2> b> {
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// Operands of different bits types are allowed.
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bits<8> add = !add(a, b);
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bits<8> sub = !sub(a, b);
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bits<8> and = !and(a, b);
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bits<8> or = !or(a, b);
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bits<8> xor = !xor(a, b);
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bits<8> srl = !srl(a, b);
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bits<8> sra = !sra(a, b);
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bits<8> shl = !shl(a, b);
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}
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def A0 : A<21, 3>;
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def A1 {
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bits<8> sra = !sra(-1, 3);
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}
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