forked from OSchip/llvm-project
58 lines
1.5 KiB
TableGen
58 lines
1.5 KiB
TableGen
// RUN: llvm-tblgen -gen-emitter -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def archInstrInfo : InstrInfo { }
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def arch : Target {
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let InstructionSet = archInstrInfo;
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}
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def Myi32 : Operand<i32> {
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let DecoderMethod = "DecodeMyi32";
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}
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let OutOperandList = (outs), Size = 2 in {
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def foo : Instruction {
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let InOperandList = (ins i32imm:$factor);
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field bits<65> Inst;
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bits<32> factor;
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let Inst{7...0} = 0xAA;
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let Inst{14...8} = factor{6...0}; // no offset
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let AsmString = "foo $factor";
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field bits<16> SoftFail = 0;
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}
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def bar : Instruction {
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let InOperandList = (ins i32imm:$factor);
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field bits<65> Inst;
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bits<32> factor;
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let Inst{7...0} = 0xBB;
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let Inst{15...8} = factor{10...3}; // offset by 3
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let AsmString = "bar $factor";
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field bits<16> SoftFail = 0;
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}
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def biz : Instruction {
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let InOperandList = (ins i32imm:$factor);
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field bits<65> Inst;
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bits<32> factor;
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let Inst{7...0} = 0xCC;
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let Inst{11...8,15...12} = factor{10...3}; // offset by 3, multipart
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let AsmString = "biz $factor";
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field bits<16> SoftFail = 0;
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}
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}
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// CHECK-LABEL: case ::biz: {
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// CHECK: Value.insertBits(op.extractBitsAsZExtValue(4, 3), 12, 4);
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// CHECK-NEXT: Value.insertBits(op.extractBitsAsZExtValue(4, 7), 8, 4);
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// CHECK-LABEL: case ::foo: {
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// CHECK: Value.insertBits(op.extractBitsAsZExtValue(7, 0), 8, 7);
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// CHECK-LABEL: case ::bar: {
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// CHECK: Value.insertBits(op.extractBitsAsZExtValue(8, 3), 8, 8);
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