forked from OSchip/llvm-project
29 lines
648 B
TableGen
29 lines
648 B
TableGen
// RUN: llvm-tblgen -gen-asm-writer -I %p/../../include %s | FileCheck %s
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include "llvm/Target/Target.td"
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def ArchInstrInfo : InstrInfo { }
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def Arch : Target {
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let InstructionSet = ArchInstrInfo;
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}
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def Reg : Register<"reg">;
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def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
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def IntOperand: Operand<i32>;
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def foo : Instruction {
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let Size = 2;
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let OutOperandList = (outs);
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let InOperandList = (ins IntOperand:$imm);
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let AsmString = "foo $imm";
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let Namespace = "Arch";
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}
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def FooBraces : InstAlias<"foo \\{$imm\\}", (foo IntOperand:$imm)>;
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// CHECK: static const char AsmStrings[] =
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// CHECK-NEXT: /* 0 */ "foo {$\x01}\0"
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