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whitequark 77ccc2eba4 [SelectionDAG] Fix return calling convention in expansion of ?MULO 
Summary:
The SMULO/UMULO DAG nodes, when not directly supported by the target,
expand to a multiplication twice as wide. In case that the resulting
type is not legal, the legalizer cannot directly call the intrinsic
with the wide arguments; instead, it "pre-lowers" them by splitting
them in halves.

rL283203 made sure that on big endian targets, the legalizer passes
the argument halves in the correct order. It did not do the same
for the return value halves because the existing code used a hack;
it put an illegal type into DAG and hoped that nothing would break
and it would be correctly lowered elsewhere.

rL307207 fixed this, handling return value halves similar to how
argument handles are handled, but did not take big-endian targets
into account.

This commit fixes the expansion on big-endian targets, such as
the out-of-tree OR1K target.

Reviewers: eli.friedman, vadimcn

Subscribers: george-hopkins, efriedma, llvm-commits

Differential Revision: https://reviews.llvm.org/D45355

llvm-svn: 353854
 		2019-02-12 16:41:50 +00:00
..
2007-01-31-RegInfoAssert.ll
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2007-02-02-JoinIntervalsCrash.ll
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2007-05-05-InvalidPushPop.ll
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2009-06-18-ThumbCommuteMul.ll
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2009-07-20-TwoAddrBug.ll
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2009-07-27-PEIAssert.ll Replace "no-frame-pointer-*" function attributes with "frame-pointer" 2019-01-14 10:55:55 +00:00
2009-08-12-ConstIslandAssert.ll
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2009-08-12-RegInfoAssert.ll
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2009-08-20-ISelBug.ll Replace "no-frame-pointer-*" function attributes with "frame-pointer" 2019-01-14 10:55:55 +00:00
2009-12-17-pre-regalloc-taildup.ll
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2010-06-18-SibCallCrash.ll
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2010-07-01-FuncAlign.ll
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2010-07-15-debugOrdering.ll In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled. 2017-03-14 00:34:14 +00:00
2011-05-11-DAGLegalizer.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
2011-06-16-NoGPRs.ll
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2011-EpilogueBug.ll
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2012-04-26-M0ISelBug.ll
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2014-06-10-thumb1-ldst-opt-bug.ll
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DbgValueOtherTargets.test
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PR17309.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
PR35481.ll [ARM] Fix PR35481 2018-01-08 11:32:37 +00:00
PR36658.mir [ARM] Fix "Constant pool entry out of range!" in Thumb1 mode 2018-03-23 17:53:27 +00:00
addr-modes.ll [ARM, Thumb1] Prevent ARMTargetLowering::isLegalAddressingMode from accepting illegal modes 2017-08-24 10:00:25 +00:00
and_neg.ll
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asmprinter-bug.ll
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barrier.ll
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bic_imm.ll [ARM] Adjust AND immediates to make them cheaper to select. 2018-08-10 21:21:53 +00:00
branchless-cmp.ll [SelectionDAG] swap select_cc operands to enable folding 2018-11-09 11:09:40 +00:00
callee_save.ll
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cmp-add-fold.ll In Thumb1 mode, the custom lowering for ARMISD::CMPZ could never emit tADDi3 2017-02-17 18:59:16 +00:00
cmp-fold.ll
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constants.ll [ARM] Materialise some boolean values to avoid a branch 2018-02-16 09:23:59 +00:00
consthoist-few-dependents.ll [ARM] Make InstrEmitter mark CPSR defs dead for Thumb1. 2018-10-26 19:32:24 +00:00
consthoist-imm8-costs-1.ll [Thumb1] Any imm8 should have cost of 1 2018-09-24 16:15:23 +00:00
copy_thumb.ll In Thumb1, materialize a move between low registers as a `movs`, if CPSR isn't live. 2017-03-07 09:38:16 +00:00
cortex-m0-unaligned-access.ll
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dyn-stackalloc.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
fastcc.ll
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fpconv.ll
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fpow.ll
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frame-access.ll Replace "no-frame-pointer-*" function attributes with "frame-pointer" 2019-01-14 10:55:55 +00:00
frame_thumb.ll Replace "no-frame-pointer-*" function attributes with "frame-pointer" 2019-01-14 10:55:55 +00:00
i8-phi-ext.ll [CodeGen] Emit more precise AssertZext/AssertSext nodes. 2018-07-11 23:26:35 +00:00
iabs.ll
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inlineasm-imm-thumb.ll
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inlineasm-thumb.ll
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ispositive.ll [ARM] t2_so_imm_neg had a subtle bug in the conversion, and could trigger UB by negating (int)-2147483648. By pure luck, none of the pre-existing tests triggered this; so I'm adding one. 2017-03-22 15:09:30 +00:00
large-stack.ll [ARM] Dynamic stack alignment for 16-bit Thumb 2017-10-22 11:56:35 +00:00
ldm-merge-call.ll
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ldm-merge-struct.ll
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ldm-stm-base-materialization-thumb2.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
ldm-stm-base-materialization.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
ldm-stm-postinc.ll
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ldr_ext.ll
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ldr_frame.ll
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lit.local.cfg
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litpoolremat.ll [ARM] Allow rematerialization of ARM Thumb literal pool loads 2017-07-14 08:23:56 +00:00
long-setcc.ll [ARM] Add missing pseudo-instruction for Thumb1 RSBS. 2018-10-31 21:45:48 +00:00
long.ll [ARM] Return true in enableMultipleCopyHints(). 2018-02-16 09:51:01 +00:00
long_shift.ll
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machine-cse-physreg.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
mature-mc-support.ll [LLC] Add an inline assembly diagnostics handler. 2017-02-03 11:14:39 +00:00
mul.ll
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mvn.ll [ARM] Fix issue with large xor constants. 2018-02-22 09:38:57 +00:00
opt-phis.mir [Codegen] Make sure kill flags are not incorrect from removed machine phi's 2019-02-12 15:02:57 +00:00
optionaldef-scheduling.ll [ARM] ScheduleDAGRRList::DelayForLiveRegsBottomUp must consider OptionalDefs 2017-04-23 06:58:08 +00:00
pop.ll
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pr35836.ll Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding" 2018-02-27 16:59:10 +00:00
pr35836_2.ll [ARM] Allow the scheduler to clone a node with glue to avoid a copy CPSR ↔ GPR. 2018-01-31 09:23:43 +00:00
push.ll Replace "no-frame-pointer-*" function attributes with "frame-pointer" 2019-01-14 10:55:55 +00:00
ragreedy-implicit-def.ll [RegAllocGreedy] IMPLICIT_DEF values shouldn't prefer registers 2018-12-14 14:07:57 +00:00
remove-unneeded-push-pop.ll [ARM] Fix constant islands pass. 2017-02-22 09:06:21 +00:00
rev.ll
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segmented-stacks-dynamic.ll
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segmented-stacks.ll
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select.ll [ARM] Fix CPSR liveness in tMOVCCr_pseudo lowering. 2018-11-07 21:08:13 +00:00
shift-and.ll [ARM] Combine ands+lsls to lsls+lsrs for Thumb1. 2019-01-22 01:51:37 +00:00
sjljehprepare-lower-vector.ll
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stack-access.ll Elide stores which are overwritten without being observed. 2017-05-16 19:43:56 +00:00
stack-coloring-without-frame-ptr.ll Remove alignment argument from memcpy/memmove/memset in favour of alignment attributes (Step 1) 2018-01-19 17:13:12 +00:00
stack-frame.ll
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stack_guard_remat.ll Add address space mangling to lifetime intrinsics 2017-04-10 20:18:21 +00:00
stm-deprecated.ll [ARM] Don't generate deprecated T1 STM. 2017-02-28 23:32:55 +00:00
stm-merge.ll
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stm-scavenging.ll [LivePhysRegs] Fix handling of return instructions. 2018-02-06 23:00:17 +00:00
tbb-reuse.mir Followup on Proposal to move MIR physical register namespace to '$' sigil. 2018-01-31 22:04:26 +00:00
thumb-imm.ll
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thumb-ldm.ll
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thumb-shrink-wrapping.ll [ARM] Allow CMPZ transforms even if the input has multiple uses. 2018-06-08 21:16:56 +00:00
thumb1-cmp.ll [ARM] Testcase for Thumb1 cmp with constants. 2018-06-19 00:12:13 +00:00
trap.ll
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triple.ll
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tst_teq.ll
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umulo-32-legalisation-lowering.ll [SelectionDAG] Fix return calling convention in expansion of ?MULO 2019-02-12 16:41:50 +00:00
umulo-128-legalisation-lowering.ll [ARM] Make InstrEmitter mark CPSR defs dead for Thumb1. 2018-10-26 19:32:24 +00:00
unord.ll
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uxth.ll [ARM] Mark 255 and 65535 as cheap for Thumb1 "And" 2019-02-04 11:58:48 +00:00
vargs.ll
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