forked from OSchip/llvm-project
111 lines
3.5 KiB
C++
111 lines
3.5 KiB
C++
//===- ARM64Common.cpp ----------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "Arch/ARM64Common.h"
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#include "lld/Common/ErrorHandler.h"
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#include "llvm/Support/Endian.h"
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using namespace llvm::MachO;
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using namespace llvm::support::endian;
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using namespace lld;
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using namespace lld::macho;
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int64_t ARM64Common::getEmbeddedAddend(MemoryBufferRef mb, uint64_t offset,
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const relocation_info rel) const {
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if (rel.r_type != ARM64_RELOC_UNSIGNED &&
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rel.r_type != ARM64_RELOC_SUBTRACTOR) {
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// All other reloc types should use the ADDEND relocation to store their
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// addends.
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// TODO(gkm): extract embedded addend just so we can assert that it is 0
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return 0;
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}
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const auto *buf = reinterpret_cast<const uint8_t *>(mb.getBufferStart());
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const uint8_t *loc = buf + offset + rel.r_address;
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switch (rel.r_length) {
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case 2:
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return static_cast<int32_t>(read32le(loc));
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case 3:
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return read64le(loc);
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default:
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llvm_unreachable("invalid r_length");
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}
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}
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// For instruction relocations (load, store, add), the base
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// instruction is pre-populated in the text section. A pre-populated
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// instruction has opcode & register-operand bits set, with immediate
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// operands zeroed. We read it from text, OR-in the immediate
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// operands, then write-back the completed instruction.
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void ARM64Common::relocateOne(uint8_t *loc, const Reloc &r, uint64_t value,
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uint64_t pc) const {
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uint32_t base = ((r.length == 2) ? read32le(loc) : 0);
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switch (r.type) {
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case ARM64_RELOC_BRANCH26:
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value = encodeBranch26(r, base, value - pc);
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break;
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case ARM64_RELOC_SUBTRACTOR:
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case ARM64_RELOC_UNSIGNED:
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if (r.length == 2)
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checkInt(r, value, 32);
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break;
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case ARM64_RELOC_POINTER_TO_GOT:
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if (r.pcrel)
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value -= pc;
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checkInt(r, value, 32);
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break;
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case ARM64_RELOC_PAGE21:
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case ARM64_RELOC_GOT_LOAD_PAGE21:
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case ARM64_RELOC_TLVP_LOAD_PAGE21: {
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assert(r.pcrel);
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value = encodePage21(r, base, pageBits(value) - pageBits(pc));
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break;
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}
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case ARM64_RELOC_PAGEOFF12:
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case ARM64_RELOC_GOT_LOAD_PAGEOFF12:
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case ARM64_RELOC_TLVP_LOAD_PAGEOFF12:
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assert(!r.pcrel);
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value = encodePageOff12(base, value);
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break;
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default:
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llvm_unreachable("unexpected relocation type");
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}
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switch (r.length) {
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case 2:
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write32le(loc, value);
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break;
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case 3:
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write64le(loc, value);
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break;
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default:
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llvm_unreachable("invalid r_length");
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}
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}
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void ARM64Common::relaxGotLoad(uint8_t *loc, uint8_t type) const {
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// The instruction format comments below are quoted from
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// Arm® Architecture Reference Manual
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// Armv8, for Armv8-A architecture profile
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// ARM DDI 0487G.a (ID011921)
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uint32_t instruction = read32le(loc);
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// C6.2.132 LDR (immediate)
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// This matches both the 64- and 32-bit variants:
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// LDR <(X|W)t>, [<Xn|SP>{, #<pimm>}]
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if ((instruction & 0xbfc00000) != 0xb9400000)
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error(getRelocAttrs(type).name + " reloc requires LDR instruction");
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assert(((instruction >> 10) & 0xfff) == 0 &&
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"non-zero embedded LDR immediate");
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// C6.2.4 ADD (immediate)
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// ADD <Xd|SP>, <Xn|SP>, #<imm>{, <shift>}
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instruction = ((instruction & 0x001fffff) | 0x91000000);
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write32le(loc, instruction);
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}
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