Chen Zheng c8f6c0f961 [Machinesink] add one more profitable loop related pattern ... Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D86925		2020-09-26 21:02:21 -04:00
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Analysis	Revert "[DSE] Switch to MemorySSA-backed DSE by default."	2020-09-26 18:35:27 +01:00
Assembler	OpaquePtr: Add type to sret attribute	2020-09-25 14:07:30 -04:00
Bindings	C API: functions to get mask of a ShuffleVector	2020-09-25 16:01:05 -07:00
Bitcode	OpaquePtr: Add type to sret attribute	2020-09-25 14:07:30 -04:00
BugPoint	…
CodeGen	[Machinesink] add one more profitable loop related pattern	2020-09-26 21:02:21 -04:00
DebugInfo	Add a verifier check that rejects non-distinct DISubprogram function	2020-09-25 12:04:46 -07:00
Demangle	…
Examples	…
ExecutionEngine	…
Feature	…
FileCheck	…
Instrumentation	…
Integer	…
JitListener	…
LTO	…
Linker	…
MC	[PowerPC] Add accumulator register class and instructions	2020-09-25 12:25:13 -05:00
MachineVerifier	…
Object	[Object/yaml2obj/obj2yaml][test] - Split, cleanup and move MIPS abi-flags.yaml test. NFCI.	2020-09-25 12:04:55 +03:00
ObjectYAML	…
Other	Revert "[DSE] Switch to MemorySSA-backed DSE by default."	2020-09-26 18:35:27 +01:00
Reduce	…
SafepointIRVerifier	…
Support	…
SymbolRewriter	…
TableGen	…
ThinLTO/X86	…
Transforms	[InstCombine] Add basic vector test coverage for icmp_eq/ne zero combines	2020-09-26 20:09:11 +01:00
Unit	…
Verifier	Add a verifier check that rejects non-distinct DISubprogram function	2020-09-25 12:04:46 -07:00
YAMLParser	…
tools	Revert "[IRSim] Adding basic implementation of llvm-sim."	2020-09-25 16:18:48 -05:00
.clang-format	…
CMakeLists.txt	…
TestRunner.sh	…
lit.cfg.py	…
lit.site.cfg.py.in	…