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llvm-project/llvm/lib/Target/AMDGPU
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Matt Arsenault 21bc8e5a13 AMDGPU: Make VReg_1 only include 1 artificial register 
When TableGen is inferring register classes from contexts, it uses a
sorting function based on the number of registers in the class. Since
this was being treated as an alias of VGPR_32, they had exactly the
same size. The sort used wasn't a stable sort, and even if it were, I
believe the tie breaker would effectively end up being the
alphabetical ordering of the class name. There appear to be issues
trying to use an empty set of registers, so add only one so this will
always sort to the end.

Also add a comment explaining how VReg_1 is a dirty hack for
SelectionDAG.

This does end up changing the behavior of i1 with inline asm and VGPR
constraints, but the existing behavior was was already nonsensical and
inconsistent. It should probably be disallowed anyway.

Fixes bug 43699
 		2019-10-28 20:51:51 -07:00
..
AsmParser [AMDGPU][MC][GFX9] Corrected parsing of v_cndmask_b32_sdwa 2019-10-18 13:31:53 +00:00
Disassembler [AMDGPU][MC][GFX10][WS32] Corrected decoding of dst operand for v_cmp_*_sdwa opcodes 2019-10-04 13:04:17 +00:00
MCTargetDesc [Mips] Use appropriate private label prefix based on Mips ABI 2019-10-23 12:24:35 +02:00
TargetInfo Revert CMake: Make most target symbols hidden by default 2019-06-11 03:21:13 +00:00
Utils Prune two MachineInstr.h includes, fix up deps 2019-10-19 00:22:07 +00:00
AMDGPU.h [AMDGPU] Printf runtime binding pass 2019-08-12 17:12:29 +00:00
AMDGPU.td [AMDGPU] w/a for gfx908 mfma SrcC literal HW bug 2019-08-23 22:09:58 +00:00
AMDGPUAliasAnalysis.cpp AMDGPU: Improve alias analysis for GDS 2019-07-17 11:22:19 +00:00
AMDGPUAliasAnalysis.h [AliasAnalysis] Second prototype to cache BasicAA / anyAA state. 2019-03-22 17:22:19 +00:00
AMDGPUAlwaysInlinePass.cpp
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AMDGPUAnnotateKernelFeatures.cpp Use llvm::StringLiteral instead of StringRef in few places 2019-09-20 14:31:42 +00:00
AMDGPUAnnotateUniformValues.cpp
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AMDGPUArgumentUsageInfo.cpp [AMDGPU] Packed thread ids in function call ABI 2019-06-28 01:52:13 +00:00
AMDGPUArgumentUsageInfo.h AMDGPU: Fix Register copypaste error 2019-09-05 23:07:10 +00:00
AMDGPUAsmPrinter.cpp [Alignment] Migrate Attribute::getWith(Stack)Alignment 2019-10-15 12:56:24 +00:00
AMDGPUAsmPrinter.h [AMDGPU] separate accounting for agprs 2019-10-02 00:26:58 +00:00
AMDGPUAtomicOptimizer.cpp [AMDGPU] gfx10 atomic optimizer changes. 2019-08-23 10:07:43 +00:00
AMDGPUCallLowering.cpp [GISel][CallLowering] Make isIncomingArgumentHandler a pure virtual method 2019-10-18 20:13:42 +00:00
AMDGPUCallLowering.h AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC 2019-09-09 23:06:13 +00:00
AMDGPUCallingConv.td [AMDGPU] Adjust number of SGPRs available in Calling Convention 2019-08-28 15:00:45 +00:00
AMDGPUCodeGenPrepare.cpp AMDGPU: Preserve value name when inserting mul24 intrinsic 2019-08-24 22:17:10 +00:00
AMDGPUFeatures.td AMDGPU: Fix names for generation features 2019-04-03 00:01:03 +00:00
AMDGPUFixFunctionBitcasts.cpp
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AMDGPUFrameLowering.cpp Use Align for TFL::TransientStackAlignment 2019-10-21 08:31:25 +00:00
AMDGPUFrameLowering.h Use Align for TFL::TransientStackAlignment 2019-10-21 08:31:25 +00:00
AMDGPUGISel.td AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG 2019-10-25 13:11:09 -07:00
AMDGPUGenRegisterBankInfo.def AMDGPU/GlobalISel: Fix RegBankSelect for 1024-bit values 2019-10-02 01:02:14 +00:00
AMDGPUHSAMetadataStreamer.cpp [Alignment] Migrate Attribute::getWith(Stack)Alignment 2019-10-15 12:56:24 +00:00
AMDGPUHSAMetadataStreamer.h [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
AMDGPUISelDAGToDAG.cpp AMDGPU: Slightly restructure m0 init code 2019-10-21 19:42:26 +00:00
AMDGPUISelLowering.cpp AMDGPU: Select basic interp directly from intrinsics 2019-10-21 21:49:44 +00:00
AMDGPUISelLowering.h AMDGPU: Select basic interp directly from intrinsics 2019-10-21 21:49:44 +00:00
AMDGPUInline.cpp [AMDGPU] Improve code size cost model 2019-10-17 12:15:35 +00:00
AMDGPUInstrInfo.cpp
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AMDGPUInstrInfo.h
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AMDGPUInstrInfo.td AMDGPU: Select basic interp directly from intrinsics 2019-10-21 21:49:44 +00:00
AMDGPUInstructionSelector.cpp AMDGPU: Relax 32-bit SGPR register class 2019-10-18 18:26:37 +00:00
AMDGPUInstructionSelector.h AMDGPU/GlobalISel: Select s1 src G_SITOFP/G_UITOFP 2019-10-01 02:23:20 +00:00
AMDGPUInstructions.td AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG 2019-10-25 13:11:09 -07:00
AMDGPULegalizerInfo.cpp AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG 2019-10-25 13:11:09 -07:00
AMDGPULegalizerInfo.h AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG 2019-10-25 13:11:09 -07:00
AMDGPULibCalls.cpp [NFC] Remove redundant lines 2019-10-24 19:54:28 +03:00
AMDGPULibFunc.cpp [AMDGPU] Downgrade from StringLiteral to const char* in an attempt to make GCC 5 happy 2019-08-25 12:47:31 +00:00
AMDGPULibFunc.h
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AMDGPULowerIntrinsics.cpp
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AMDGPULowerKernelArguments.cpp [Alignment] Migrate Attribute::getWith(Stack)Alignment 2019-10-15 12:56:24 +00:00
AMDGPULowerKernelAttributes.cpp
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AMDGPUMCInstLower.cpp [AMDGPU] link dpp pseudos and real instructions on gfx10 2019-10-11 22:03:36 +00:00
AMDGPUMachineCFGStructurizer.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
AMDGPUMachineFunction.cpp [Alignment] Migrate Attribute::getWith(Stack)Alignment 2019-10-15 12:56:24 +00:00
AMDGPUMachineFunction.h [Alignment] Migrate Attribute::getWith(Stack)Alignment 2019-10-15 12:56:24 +00:00
AMDGPUMachineModuleInfo.cpp AMDGPU: Add support for cross address space synchronization scopes 2019-03-25 20:50:21 +00:00
AMDGPUMachineModuleInfo.h AMDGPU: Add support for cross address space synchronization scopes 2019-03-25 20:50:21 +00:00
AMDGPUMacroFusion.cpp
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AMDGPUMacroFusion.h
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AMDGPUOpenCLEnqueuedBlockLowering.cpp Fix parameter name comments using clang-tidy. NFC. 2019-07-16 04:46:31 +00:00
AMDGPUPTNote.h
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AMDGPUPerfHintAnalysis.cpp AMDGPU: Fix assert in clang test 2019-07-05 21:09:53 +00:00
AMDGPUPerfHintAnalysis.h AMDGPU: Make AMDGPUPerfHintAnalysis an SCC pass 2019-07-05 20:26:13 +00:00
AMDGPUPrintfRuntimeBinding.cpp [AMDGPU] Make printf lowering faster when there are no printfs 2019-10-02 08:44:15 +00:00
AMDGPUPromoteAlloca.cpp [Alignment][NFC] Remove dependency on GlobalObject::setAlignment(unsigned) 2019-10-15 11:24:36 +00:00
AMDGPUPropagateAttributes.cpp AMDGPU: Move DEBUG_TYPE definition below includes 2019-07-08 18:48:39 +00:00
AMDGPURegisterBankInfo.cpp AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG 2019-10-25 13:11:09 -07:00
AMDGPURegisterBankInfo.h AMDGPU/GlobalISel: Split 64-bit vector extracts during RegBankSelect 2019-10-03 17:55:27 +00:00
AMDGPURegisterBanks.td AMDGPU/GlobalISel: Increase max legal size to 1024 2019-10-01 16:35:06 +00:00
AMDGPURegisterInfo.cpp AMDGPU/GlobalISel: Handle more G_INSERT cases 2019-10-07 19:16:26 +00:00
AMDGPURegisterInfo.h AMDGPU/GlobalISel: Handle more G_INSERT cases 2019-10-07 19:16:26 +00:00
AMDGPURegisterInfo.td [AMDGPU] gfx908 register file changes 2019-07-09 19:41:51 +00:00
AMDGPURewriteOutArguments.cpp
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AMDGPUSearchableTables.td AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec} 2019-08-05 09:36:06 +00:00
AMDGPUSubtarget.cpp [AMDGPU] Fix mfma scheduling crash 2019-10-24 11:01:52 -07:00
AMDGPUSubtarget.h [Alignment][NFC] Use Align for TargetFrameLowering/Subtarget 2019-10-17 07:49:39 +00:00
AMDGPUTargetMachine.cpp Revert "[AMDGPU] Run `unreachable-mbb-elimination` after isel to clean up PHIs." 2019-10-10 13:34:31 +00:00
AMDGPUTargetMachine.h MIR: Allow targets to serialize MachineFunctionInfo 2019-03-14 22:54:43 +00:00
AMDGPUTargetObjectFile.cpp
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AMDGPUTargetObjectFile.h
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AMDGPUTargetTransformInfo.cpp [AMDGPU] Improve code size cost model 2019-10-17 12:15:35 +00:00
AMDGPUTargetTransformInfo.h [AMDGPU] Improve code size cost model 2019-10-17 12:15:35 +00:00
AMDGPUUnifyDivergentExitNodes.cpp Update phis in AMDGPUUnifyDivergentExitNodes 2019-06-25 18:55:16 +00:00
AMDGPUUnifyMetadata.cpp
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AMDILCFGStructurizer.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
AMDKernelCodeT.h [AMDGPU] gfx1010 wave32 metadata 2019-06-17 16:48:56 +00:00
BUFInstructions.td [AMDGPU] drop getIsFP td helper 2019-10-17 21:46:56 +00:00
CMakeLists.txt [AMDGPU] Printf runtime binding pass 2019-08-12 17:12:29 +00:00
CaymanInstructions.td
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DSInstructions.td [AMDGPU][MC][GFX9][GFX10] Corrected number of src operands for ds_[read/write]_addtid_b32 2019-10-11 14:53:26 +00:00
EvergreenInstructions.td AMDGPU: Start redefining atomic PatFrags 2019-08-01 03:25:52 +00:00
FLATInstructions.td AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG 2019-10-25 13:11:09 -07:00
GCNDPPCombine.cpp [AMDGPU] Disallow dpp combining for dpp instructions without Src2 operand (when Src2 is required) 2019-10-25 21:30:37 +03:00
GCNHazardRecognizer.cpp AMDGPU: Fix SMEM WAR hazard for gfx10 readlane 2019-10-18 18:20:30 +00:00
GCNHazardRecognizer.h [AMDGPU] gfx908 hazard recognizer 2019-07-11 21:30:34 +00:00
GCNILPSched.cpp Prune a LegacyDivergenceAnalysis and MachineLoopInfo include each 2019-10-19 01:31:09 +00:00
GCNIterativeScheduler.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
GCNIterativeScheduler.h
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GCNMinRegStrategy.cpp
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GCNNSAReassign.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
GCNProcessors.td [AMDGPU] gfx908 target 2019-07-09 18:10:06 +00:00
GCNRegBankReassign.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
GCNRegPressure.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
GCNRegPressure.h Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
GCNSchedStrategy.cpp [AMDGPU] Add VerifyScheduling support. 2019-10-01 15:45:47 +00:00
GCNSchedStrategy.h AMDGPU: Avoid constructing new std::vector in initCandidate 2019-09-05 22:44:06 +00:00
LLVMBuild.txt [AMDGPU] Move InstPrinter files to MCTargetDesc. NFC 2019-05-11 00:03:35 +00:00
MIMGInstructions.td [AMDGPU] Use PredicateControl in MIMGBaseOpcode. NFC. 2019-08-12 22:32:21 +00:00
R600.td
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R600AsmPrinter.cpp [Alignment][NFC] Remove unneeded llvm:: scoping on Align types 2019-09-27 12:54:21 +00:00
R600AsmPrinter.h
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R600ClauseMergePass.cpp
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R600ControlFlowFinalizer.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
R600Defines.h
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R600EmitClauseMarkers.cpp
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R600ExpandSpecialInstrs.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
R600FrameLowering.cpp
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R600FrameLowering.h Use Align for TFL::TransientStackAlignment 2019-10-21 08:31:25 +00:00
R600ISelLowering.cpp [AMDGPU] Use math constants defined in MathExtras (NFC) 2019-10-09 20:00:43 +00:00
R600ISelLowering.h [TargetLowering] Add MachineMemOperand::Flags to allowsMemoryAccess tests (PR42123) 2019-06-12 17:14:03 +00:00
R600InstrFormats.td
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R600InstrInfo.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
R600InstrInfo.h
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R600Instructions.td AMDGPU: Redefine load PatFrags 2019-07-16 17:38:50 +00:00
R600MachineFunctionInfo.cpp
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R600MachineFunctionInfo.h
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R600MachineScheduler.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
R600MachineScheduler.h
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R600OpenCLImageTypeLoweringPass.cpp
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R600OptimizeVectorRegisters.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
R600Packetizer.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
R600Processors.td AMDGPU: Fix names for generation features 2019-04-03 00:01:03 +00:00
R600RegisterInfo.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
R600RegisterInfo.h CodeGen: Introduce a class for registers 2019-06-24 15:50:29 +00:00
R600RegisterInfo.td
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R600Schedule.td
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R700Instructions.td
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SIAddIMGInit.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
SIAnnotateControlFlow.cpp [AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32 2019-06-13 23:47:36 +00:00
SIDefines.h [AMDGPU] Added MI bit IsDOT 2019-09-17 17:56:13 +00:00
SIFixSGPRCopies.cpp [AMDGPU] move PHI nodes to AGPR class 2019-10-18 22:48:45 +00:00
SIFixVGPRCopies.cpp
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SIFixupVectorISel.cpp Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC 2019-08-01 23:27:28 +00:00
SIFoldOperands.cpp [AMDGPU] Enable SGPR copy folding 2019-10-25 15:08:30 -07:00
SIFormMemoryClauses.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
SIFrameLowering.cpp [AArch64] Static (de)allocation of SVE stack objects. 2019-10-03 11:33:50 +00:00
SIFrameLowering.h Use Align for TFL::TransientStackAlignment 2019-10-21 08:31:25 +00:00
SIISelLowering.cpp AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG 2019-10-25 13:11:09 -07:00
SIISelLowering.h AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG 2019-10-25 13:11:09 -07:00
SIInsertSkips.cpp [AMDGPU] gfx10 conditional registers handling 2019-06-16 17:13:09 +00:00
SIInsertWaitcnts.cpp AMDGPU: Avoid overwriting saved PC 2019-10-28 10:02:22 -07:00
SIInstrFormats.td [AMDGPU] Added MI bit IsDOT 2019-09-17 17:56:13 +00:00
SIInstrInfo.cpp [AMDGPU] Enable SGPR copy folding 2019-10-25 15:08:30 -07:00
SIInstrInfo.h AMDGPU: Split flat offsets that don't fit in DAG 2019-10-20 17:34:44 +00:00
SIInstrInfo.td AMDGPU: Fix missing OPERAND_IMMEDIATE 2019-10-20 16:56:10 +00:00
SIInstructions.td AMDGPU/GlobalISel: Handle flat/global G_ATOMIC_CMPXCHG 2019-10-25 13:11:09 -07:00
SILoadStoreOptimizer.cpp [AMDGPU] Extend the SI Load/Store optimizer 2019-10-16 10:17:02 +00:00
SILowerControlFlow.cpp [AMDGPU]: PHI Elimination hooks added for custom COPY insertion. Fixed 2019-09-17 09:08:58 +00:00
SILowerI1Copies.cpp [AMDGPU] Fix Vreg_1 PHI lowering in SILowerI1Copies. 2019-10-26 14:37:45 +05:30
SILowerSGPRSpills.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
SIMachineFunctionInfo.cpp [Alignment] Migrate Attribute::getWith(Stack)Alignment 2019-10-15 12:56:24 +00:00
SIMachineFunctionInfo.h AMDGPU: Add amdgpu-32bit-address-high-bits to MIR serialization 2019-08-27 18:18:38 +00:00
SIMachineScheduler.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
SIMachineScheduler.h
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SIMemoryLegalizer.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
SIModeRegister.cpp [llvm] Migrate llvm::make_unique to std::make_unique 2019-08-15 15:54:37 +00:00
SIOptimizeExecMasking.cpp Revert "AMDGPU: Fix iterator error when lowering SI_END_CF" 2019-08-20 17:45:25 +00:00
SIOptimizeExecMaskingPreRA.cpp AMDGPU: Propagate undef flag during pre-RA exec mask optimizations 2019-10-08 12:46:32 +00:00
SIPeepholeSDWA.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
SIPreAllocateWWMRegs.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
SIProgramInfo.h [AMDGPU] separate accounting for agprs 2019-10-02 00:26:58 +00:00
SIRegisterInfo.cpp Fix buildbot error in SIRegisterInfo.cpp. 2019-10-20 20:01:16 +00:00
SIRegisterInfo.h [AMDGPU] Remove -amdgpu-spill-sgpr-to-smem. 2019-10-18 21:48:22 +00:00
SIRegisterInfo.td AMDGPU: Make VReg_1 only include 1 artificial register 2019-10-28 20:51:51 -07:00
SISchedule.td [AMDGPU] gfx908 scheduling 2019-07-11 21:25:00 +00:00
SIShrinkInstructions.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
SIWholeQuadMode.cpp Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM 2019-08-15 19:22:08 +00:00
SMInstructions.td AMDGPU/GlobalISel: Select SMRD loads for more types 2019-09-16 00:54:07 +00:00
SOPInstructions.td AMDGPU/GlobalISel: Allow selection of scalar min/max 2019-09-21 02:37:33 +00:00
VIInstrFormats.td
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VIInstructions.td
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VOP1Instructions.td [AMDGPU] Supress unused sdwa insts generation 2019-10-16 16:58:06 +00:00
VOP2Instructions.td [AMDGPU][MC][GFX10] Added sdwa/dpp versions of v_cndmask_b32 2019-10-18 14:49:53 +00:00
VOP3Instructions.td [AMDGPU][MC][GFX10] Added v_interp_[p1/p2/mov]_f32_e64 2019-10-28 15:03:43 +03:00
VOP3PInstructions.td [AMDGPU] Added MI bit IsDOT 2019-09-17 17:56:13 +00:00
VOPCInstructions.td [AMDGPU] Supress unused sdwa insts generation 2019-10-16 16:58:06 +00:00
VOPInstructions.td [AMDGPU] copy OtherPredicates from pseudo to VOP3_Real 2019-09-26 21:06:17 +00:00