forked from OSchip/llvm-project
58 lines
2.2 KiB
LLVM
58 lines
2.2 KiB
LLVM
; RUN: opt %loadPolly -basicaa -polly-detect -polly-allow-nonaffine-branches -polly-allow-nonaffine-loops=false -analyze < %s | FileCheck %s --check-prefix=REJECTNONAFFINELOOPS
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; RUN: opt %loadPolly -basicaa -polly-detect -polly-allow-nonaffine-branches -polly-allow-nonaffine-loops=true -analyze < %s | FileCheck %s --check-prefix=ALLOWNONAFFINELOOPS
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; RUN: opt %loadPolly -basicaa -polly-detect -polly-allow-nonaffine -polly-allow-nonaffine-branches -polly-allow-nonaffine-loops=true -analyze < %s | FileCheck %s --check-prefix=ALLOWNONAFFINELOOPSANDACCESSES
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;
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; Here we have a non-affine loop but also a non-affine access which should
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; be rejected as long as -polly-allow-nonaffine isn't given.
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;
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; REJECTNONAFFINELOOPS-NOT: Valid
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; ALLOWNONAFFINELOOPS-NOT: Valid
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; ALLOWNONAFFINELOOPSANDACCESSES: Valid Region for Scop: bb1 => bb13
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;
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; void f(int * restrict A, int * restrict C) {
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; int j;
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; for (int i = 0; i < 1024; i++) {
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; while ((j = C[i]))
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; A[j]++;
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; }
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; }
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;
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define void @f(i32* noalias %A, i32* noalias %C) {
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bb:
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br label %bb1
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bb1: ; preds = %bb12, %bb
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%indvars.iv = phi i64 [ %indvars.iv.next, %bb12 ], [ 0, %bb ]
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%exitcond = icmp ne i64 %indvars.iv, 1024
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br i1 %exitcond, label %bb2, label %bb13
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bb2: ; preds = %bb1
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br label %bb3
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bb3: ; preds = %bb6, %bb2
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%tmp = getelementptr inbounds i32, i32* %C, i64 %indvars.iv
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%tmp4 = load i32, i32* %tmp, align 4
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%tmp5 = icmp eq i32 %tmp4, 0
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br i1 %tmp5, label %bb11, label %bb6
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bb6: ; preds = %bb3
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%tmp7 = sext i32 %tmp4 to i64
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%tmp8 = getelementptr inbounds i32, i32* %A, i64 %tmp7
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%tmp9 = load i32, i32* %tmp8, align 4
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%tmp10 = add nsw i32 %tmp9, 1
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store i32 %tmp10, i32* %tmp8, align 4
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br label %bb3
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bb11: ; preds = %bb3
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br label %bb12
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bb12: ; preds = %bb11
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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br label %bb1
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bb13: ; preds = %bb1
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ret void
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}
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