forked from OSchip/llvm-project
372 lines
10 KiB
C++
372 lines
10 KiB
C++
//===-- SILowerControlFlow.cpp - Use predicates for control flow ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief This pass lowers the pseudo control flow instructions to real
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/// machine instructions.
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///
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/// All control flow is handled using predicated instructions and
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/// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
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/// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
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/// by writting to the 64-bit EXEC register (each bit corresponds to a
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/// single vector ALU). Typically, for predicates, a vector ALU will write
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/// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
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/// Vector ALU) and then the ScalarALU will AND the VCC register with the
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/// EXEC to update the predicates.
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///
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/// For example:
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/// %VCC = V_CMP_GT_F32 %VGPR1, %VGPR2
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/// %SGPR0 = SI_IF %VCC
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/// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0
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/// %SGPR0 = SI_ELSE %SGPR0
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/// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR0
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/// SI_END_CF %SGPR0
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///
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/// becomes:
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///
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/// %SGPR0 = S_AND_SAVEEXEC_B64 %VCC // Save and update the exec mask
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/// %SGPR0 = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
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/// S_CBRANCH_EXECZ label0 // This instruction is an optional
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/// // optimization which allows us to
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/// // branch if all the bits of
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/// // EXEC are zero.
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/// %VGPR0 = V_ADD_F32 %VGPR0, %VGPR0 // Do the IF block of the branch
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///
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/// label0:
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/// %SGPR0 = S_OR_SAVEEXEC_B64 %EXEC // Restore the exec mask for the Then block
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/// %EXEC = S_XOR_B64 %SGPR0, %EXEC // Clear live bits from saved exec mask
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/// S_BRANCH_EXECZ label1 // Use our branch optimization
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/// // instruction again.
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/// %VGPR0 = V_SUB_F32 %VGPR0, %VGPR // Do the THEN block
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/// label1:
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/// %EXEC = S_OR_B64 %EXEC, %SGPR0 // Re-enable saved exec mask bits
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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namespace {
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class SILowerControlFlowPass : public MachineFunctionPass {
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private:
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static const unsigned SkipThreshold = 12;
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static char ID;
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const TargetInstrInfo *TII;
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bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
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void Skip(MachineInstr &From, MachineOperand &To);
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void SkipIfDead(MachineInstr &MI);
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void If(MachineInstr &MI);
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void Else(MachineInstr &MI);
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void Break(MachineInstr &MI);
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void IfBreak(MachineInstr &MI);
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void ElseBreak(MachineInstr &MI);
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void Loop(MachineInstr &MI);
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void EndCf(MachineInstr &MI);
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void Kill(MachineInstr &MI);
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void Branch(MachineInstr &MI);
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public:
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SILowerControlFlowPass(TargetMachine &tm) :
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MachineFunctionPass(ID), TII(tm.getInstrInfo()) { }
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virtual bool runOnMachineFunction(MachineFunction &MF);
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const char *getPassName() const {
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return "SI Lower control flow instructions";
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}
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};
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} // End anonymous namespace
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char SILowerControlFlowPass::ID = 0;
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FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) {
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return new SILowerControlFlowPass(tm);
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}
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bool SILowerControlFlowPass::shouldSkip(MachineBasicBlock *From,
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MachineBasicBlock *To) {
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unsigned NumInstr = 0;
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for (MachineBasicBlock *MBB = From; MBB != To && !MBB->succ_empty();
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MBB = *MBB->succ_begin()) {
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end();
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NumInstr < SkipThreshold && I != E; ++I) {
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if (I->isBundle() || !I->isBundled())
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if (++NumInstr >= SkipThreshold)
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return true;
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}
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}
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return false;
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}
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void SILowerControlFlowPass::Skip(MachineInstr &From, MachineOperand &To) {
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if (!shouldSkip(*From.getParent()->succ_begin(), To.getMBB()))
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return;
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DebugLoc DL = From.getDebugLoc();
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BuildMI(*From.getParent(), &From, DL, TII->get(AMDGPU::S_CBRANCH_EXECZ))
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.addOperand(To)
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.addReg(AMDGPU::EXEC);
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}
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void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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if (!shouldSkip(&MBB, &MBB.getParent()->back()))
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return;
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MachineBasicBlock::iterator Insert = &MI;
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++Insert;
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// If the exec mask is non-zero, skip the next two instructions
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BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
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.addImm(3)
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.addReg(AMDGPU::EXEC);
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// Exec mask is zero: Export to NULL target...
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BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
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.addImm(0)
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.addImm(0x09) // V_008DFC_SQ_EXP_NULL
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.addImm(0)
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.addImm(1)
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.addImm(1)
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.addReg(AMDGPU::SREG_LIT_0)
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.addReg(AMDGPU::SREG_LIT_0)
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.addReg(AMDGPU::SREG_LIT_0)
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.addReg(AMDGPU::SREG_LIT_0);
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// ... and terminate wavefront
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BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
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}
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void SILowerControlFlowPass::If(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Reg = MI.getOperand(0).getReg();
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unsigned Vcc = MI.getOperand(1).getReg();
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
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.addReg(Vcc);
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
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.addReg(AMDGPU::EXEC)
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.addReg(Reg);
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Skip(MI, MI.getOperand(2));
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::Else(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned Src = MI.getOperand(1).getReg();
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_SAVEEXEC_B64), Dst)
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.addReg(Src); // Saved EXEC
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
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.addReg(AMDGPU::EXEC)
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.addReg(Dst);
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Skip(MI, MI.getOperand(2));
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::Break(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned Src = MI.getOperand(1).getReg();
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
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.addReg(AMDGPU::EXEC)
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.addReg(Src);
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::IfBreak(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned Vcc = MI.getOperand(1).getReg();
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unsigned Src = MI.getOperand(2).getReg();
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
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.addReg(Vcc)
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.addReg(Src);
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::ElseBreak(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Dst = MI.getOperand(0).getReg();
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unsigned Saved = MI.getOperand(1).getReg();
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unsigned Src = MI.getOperand(2).getReg();
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst)
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.addReg(Saved)
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.addReg(Src);
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::Loop(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Src = MI.getOperand(0).getReg();
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_ANDN2_B64), AMDGPU::EXEC)
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.addReg(AMDGPU::EXEC)
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.addReg(Src);
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
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.addOperand(MI.getOperand(1))
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.addReg(AMDGPU::EXEC);
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::EndCf(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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unsigned Reg = MI.getOperand(0).getReg();
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BuildMI(MBB, MBB.getFirstNonPHI(), DL,
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TII->get(AMDGPU::S_OR_B64), AMDGPU::EXEC)
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.addReg(AMDGPU::EXEC)
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.addReg(Reg);
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MI.eraseFromParent();
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}
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void SILowerControlFlowPass::Branch(MachineInstr &MI) {
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MachineBasicBlock *Next = MI.getParent()->getNextNode();
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MachineBasicBlock *Target = MI.getOperand(0).getMBB();
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if (Target == Next)
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MI.eraseFromParent();
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else
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assert(0);
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}
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void SILowerControlFlowPass::Kill(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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// Kill is only allowed in pixel shaders
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assert(MBB.getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType ==
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ShaderType::PIXEL);
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// Clear this pixel from the exec mask if the operand is negative
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BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
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.addReg(AMDGPU::SREG_LIT_0)
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.addOperand(MI.getOperand(0));
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MI.eraseFromParent();
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}
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bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) {
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bool HaveKill = false;
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unsigned Depth = 0;
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for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
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BI != BE; ++BI) {
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MachineBasicBlock &MBB = *BI;
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for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
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I != MBB.end(); I = Next) {
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Next = llvm::next(I);
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MachineInstr &MI = *I;
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switch (MI.getOpcode()) {
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default: break;
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case AMDGPU::SI_IF:
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++Depth;
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If(MI);
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break;
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case AMDGPU::SI_ELSE:
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Else(MI);
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break;
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case AMDGPU::SI_BREAK:
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Break(MI);
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break;
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case AMDGPU::SI_IF_BREAK:
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IfBreak(MI);
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break;
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case AMDGPU::SI_ELSE_BREAK:
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ElseBreak(MI);
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break;
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case AMDGPU::SI_LOOP:
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++Depth;
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Loop(MI);
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break;
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case AMDGPU::SI_END_CF:
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if (--Depth == 0 && HaveKill) {
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SkipIfDead(MI);
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HaveKill = false;
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}
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EndCf(MI);
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break;
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case AMDGPU::SI_KILL:
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if (Depth == 0)
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SkipIfDead(MI);
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else
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HaveKill = true;
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Kill(MI);
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break;
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case AMDGPU::S_BRANCH:
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Branch(MI);
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break;
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}
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}
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}
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return true;
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}
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