forked from OSchip/llvm-project
298 lines
10 KiB
C++
298 lines
10 KiB
C++
//===-- AMDGPUTargetMachine.cpp - TargetMachine for hw codegen targets-----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief The AMDGPU target machine contains all of the hardware specific
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/// information needed to emit code for R600 and SI GPUs.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUTargetMachine.h"
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#include "AMDGPU.h"
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#include "AMDGPUTargetTransformInfo.h"
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#include "R600ISelLowering.h"
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#include "R600InstrInfo.h"
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#include "R600MachineScheduler.h"
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#include "SIISelLowering.h"
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#include "SIInstrInfo.h"
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#include "llvm/Analysis/Passes.h"
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#include "llvm/CodeGen/MachineFunctionAnalysis.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/IR/Verifier.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/IR/LegacyPassManager.h"
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#include "llvm/Support/TargetRegistry.h"
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#include "llvm/Support/raw_os_ostream.h"
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#include "llvm/Transforms/IPO.h"
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#include "llvm/Transforms/Scalar.h"
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#include <llvm/CodeGen/Passes.h>
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using namespace llvm;
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extern "C" void LLVMInitializeAMDGPUTarget() {
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// Register the target
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RegisterTargetMachine<R600TargetMachine> X(TheAMDGPUTarget);
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RegisterTargetMachine<GCNTargetMachine> Y(TheGCNTarget);
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}
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static ScheduleDAGInstrs *createR600MachineScheduler(MachineSchedContext *C) {
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return new ScheduleDAGMILive(C, make_unique<R600SchedStrategy>());
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}
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static MachineSchedRegistry
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SchedCustomRegistry("r600", "Run R600's custom scheduler",
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createR600MachineScheduler);
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static std::string computeDataLayout(const Triple &TT) {
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std::string Ret = "e-p:32:32";
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if (TT.getArch() == Triple::amdgcn) {
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// 32-bit private, local, and region pointers. 64-bit global and constant.
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Ret += "-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64";
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}
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Ret += "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256"
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"-v512:512-v1024:1024-v2048:2048-n32:64";
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return Ret;
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}
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AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
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StringRef CPU, StringRef FS,
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TargetOptions Options, Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OptLevel)
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: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
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OptLevel),
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TLOF(new TargetLoweringObjectFileELF()), Subtarget(TT, CPU, FS, *this),
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IntrinsicInfo() {
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setRequiresStructuredCFG(true);
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initAsmInfo();
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}
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AMDGPUTargetMachine::~AMDGPUTargetMachine() {
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delete TLOF;
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}
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//===----------------------------------------------------------------------===//
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// R600 Target Machine (R600 -> Cayman)
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//===----------------------------------------------------------------------===//
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R600TargetMachine::R600TargetMachine(const Target &T, const Triple &TT,
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StringRef FS, StringRef CPU,
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TargetOptions Options, Reloc::Model RM,
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CodeModel::Model CM, CodeGenOpt::Level OL)
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: AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
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//===----------------------------------------------------------------------===//
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// GCN Target Machine (SI+)
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//===----------------------------------------------------------------------===//
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GCNTargetMachine::GCNTargetMachine(const Target &T, const Triple &TT,
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StringRef FS, StringRef CPU,
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TargetOptions Options, Reloc::Model RM,
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CodeModel::Model CM, CodeGenOpt::Level OL)
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: AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {}
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//===----------------------------------------------------------------------===//
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// AMDGPU Pass Setup
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//===----------------------------------------------------------------------===//
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namespace {
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class AMDGPUPassConfig : public TargetPassConfig {
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public:
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AMDGPUPassConfig(TargetMachine *TM, PassManagerBase &PM)
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: TargetPassConfig(TM, PM) {}
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AMDGPUTargetMachine &getAMDGPUTargetMachine() const {
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return getTM<AMDGPUTargetMachine>();
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}
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ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const override {
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const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
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if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS)
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return createR600MachineScheduler(C);
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return nullptr;
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}
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void addIRPasses() override;
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void addCodeGenPrepare() override;
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virtual bool addPreISel() override;
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virtual bool addInstSelector() override;
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};
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class R600PassConfig : public AMDGPUPassConfig {
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public:
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R600PassConfig(TargetMachine *TM, PassManagerBase &PM)
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: AMDGPUPassConfig(TM, PM) { }
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bool addPreISel() override;
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void addPreRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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class GCNPassConfig : public AMDGPUPassConfig {
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public:
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GCNPassConfig(TargetMachine *TM, PassManagerBase &PM)
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: AMDGPUPassConfig(TM, PM) { }
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bool addPreISel() override;
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bool addInstSelector() override;
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void addPreRegAlloc() override;
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void addPostRegAlloc() override;
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void addPreSched2() override;
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void addPreEmitPass() override;
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};
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} // End of anonymous namespace
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TargetIRAnalysis AMDGPUTargetMachine::getTargetIRAnalysis() {
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return TargetIRAnalysis([this](Function &F) {
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return TargetTransformInfo(
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AMDGPUTTIImpl(this, F.getParent()->getDataLayout()));
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});
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}
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void AMDGPUPassConfig::addIRPasses() {
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// Function calls are not supported, so make sure we inline everything.
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addPass(createAMDGPUAlwaysInlinePass());
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addPass(createAlwaysInlinerPass());
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// We need to add the barrier noop pass, otherwise adding the function
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// inlining pass will cause all of the PassConfigs passes to be run
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// one function at a time, which means if we have a nodule with two
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// functions, then we will generate code for the first function
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// without ever running any passes on the second.
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addPass(createBarrierNoopPass());
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// Handle uses of OpenCL image2d_t, image3d_t and sampler_t arguments.
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addPass(createAMDGPUOpenCLImageTypeLoweringPass());
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TargetPassConfig::addIRPasses();
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}
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void AMDGPUPassConfig::addCodeGenPrepare() {
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const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
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if (ST.isPromoteAllocaEnabled()) {
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addPass(createAMDGPUPromoteAlloca(ST));
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addPass(createSROAPass());
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}
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TargetPassConfig::addCodeGenPrepare();
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}
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bool
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AMDGPUPassConfig::addPreISel() {
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const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
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addPass(createFlattenCFGPass());
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if (ST.IsIRStructurizerEnabled())
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addPass(createStructurizeCFGPass());
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return false;
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}
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bool AMDGPUPassConfig::addInstSelector() {
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addPass(createAMDGPUISelDag(getAMDGPUTargetMachine()));
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return false;
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}
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//===----------------------------------------------------------------------===//
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// R600 Pass Setup
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//===----------------------------------------------------------------------===//
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bool R600PassConfig::addPreISel() {
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AMDGPUPassConfig::addPreISel();
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addPass(createR600TextureIntrinsicsReplacer());
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return false;
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}
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void R600PassConfig::addPreRegAlloc() {
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addPass(createR600VectorRegMerger(*TM));
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}
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void R600PassConfig::addPreSched2() {
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const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
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addPass(createR600EmitClauseMarkers(), false);
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if (ST.isIfCvtEnabled())
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addPass(&IfConverterID, false);
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addPass(createR600ClauseMergePass(*TM), false);
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}
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void R600PassConfig::addPreEmitPass() {
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addPass(createAMDGPUCFGStructurizerPass(), false);
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addPass(createR600ExpandSpecialInstrsPass(*TM), false);
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addPass(&FinalizeMachineBundlesID, false);
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addPass(createR600Packetizer(*TM), false);
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addPass(createR600ControlFlowFinalizer(*TM), false);
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}
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TargetPassConfig *R600TargetMachine::createPassConfig(PassManagerBase &PM) {
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return new R600PassConfig(this, PM);
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}
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//===----------------------------------------------------------------------===//
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// GCN Pass Setup
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//===----------------------------------------------------------------------===//
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bool GCNPassConfig::addPreISel() {
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AMDGPUPassConfig::addPreISel();
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addPass(createSinkingPass());
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addPass(createSITypeRewriter());
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addPass(createSIAnnotateControlFlowPass());
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return false;
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}
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bool GCNPassConfig::addInstSelector() {
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AMDGPUPassConfig::addInstSelector();
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addPass(createSILowerI1CopiesPass());
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addPass(createSIFixSGPRCopiesPass(*TM));
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addPass(createSIFoldOperandsPass());
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return false;
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}
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void GCNPassConfig::addPreRegAlloc() {
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const AMDGPUSubtarget &ST = *getAMDGPUTargetMachine().getSubtargetImpl();
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// This needs to be run directly before register allocation because
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// earlier passes might recompute live intervals.
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// TODO: handle CodeGenOpt::None; fast RA ignores spill weights set by the pass
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if (getOptLevel() > CodeGenOpt::None) {
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initializeSIFixControlFlowLiveIntervalsPass(*PassRegistry::getPassRegistry());
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insertPass(&MachineSchedulerID, &SIFixControlFlowLiveIntervalsID);
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}
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if (getOptLevel() > CodeGenOpt::None && ST.loadStoreOptEnabled()) {
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// Don't do this with no optimizations since it throws away debug info by
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// merging nonadjacent loads.
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// This should be run after scheduling, but before register allocation. It
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// also need extra copies to the address operand to be eliminated.
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initializeSILoadStoreOptimizerPass(*PassRegistry::getPassRegistry());
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insertPass(&MachineSchedulerID, &SILoadStoreOptimizerID);
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insertPass(&MachineSchedulerID, &RegisterCoalescerID);
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}
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addPass(createSIShrinkInstructionsPass(), false);
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addPass(createSIFixSGPRLiveRangesPass());
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}
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void GCNPassConfig::addPostRegAlloc() {
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addPass(createSIPrepareScratchRegs(), false);
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addPass(createSIShrinkInstructionsPass(), false);
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}
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void GCNPassConfig::addPreSched2() {
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}
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void GCNPassConfig::addPreEmitPass() {
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addPass(createSIInsertWaits(*TM), false);
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addPass(createSILowerControlFlowPass(*TM), false);
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}
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TargetPassConfig *GCNTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new GCNPassConfig(this, PM);
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}
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