forked from OSchip/llvm-project
973 lines
46 KiB
LLVM
973 lines
46 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=avx,pclmul -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=skx -show-mc-encoding | FileCheck %s --check-prefix=CHECK --check-prefix=AVX512VL
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define <4 x double> @test_x86_avx_addsub_pd_256(<4 x double> %a0, <4 x double> %a1) {
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; CHECK-LABEL: test_x86_avx_addsub_pd_256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vaddsubpd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xd0,0xc1]
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; CHECK-NEXT: retl # encoding: [0xc3]
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%res = call <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
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ret <4 x double> %res
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}
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declare <4 x double> @llvm.x86.avx.addsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
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define <8 x float> @test_x86_avx_addsub_ps_256(<8 x float> %a0, <8 x float> %a1) {
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; CHECK-LABEL: test_x86_avx_addsub_ps_256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vaddsubps %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xff,0xd0,0xc1]
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; CHECK-NEXT: retl # encoding: [0xc3]
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%res = call <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
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ret <8 x float> %res
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}
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declare <8 x float> @llvm.x86.avx.addsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
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define <4 x double> @test_x86_avx_blendv_pd_256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) {
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; CHECK-LABEL: test_x86_avx_blendv_pd_256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vblendvpd %ymm2, %ymm1, %ymm0, %ymm0 # encoding: [0xc4,0xe3,0x7d,0x4b,0xc1,0x20]
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; CHECK-NEXT: retl # encoding: [0xc3]
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%res = call <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double> %a0, <4 x double> %a1, <4 x double> %a2) ; <<4 x double>> [#uses=1]
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ret <4 x double> %res
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}
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declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>) nounwind readnone
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define <8 x float> @test_x86_avx_blendv_ps_256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) {
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; CHECK-LABEL: test_x86_avx_blendv_ps_256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vblendvps %ymm2, %ymm1, %ymm0, %ymm0 # encoding: [0xc4,0xe3,0x7d,0x4a,0xc1,0x20]
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; CHECK-NEXT: retl # encoding: [0xc3]
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%res = call <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float> %a0, <8 x float> %a1, <8 x float> %a2) ; <<8 x float>> [#uses=1]
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ret <8 x float> %res
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}
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declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>) nounwind readnone
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define <4 x double> @test_x86_avx_cmp_pd_256(<4 x double> %a0, <4 x double> %a1) {
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; CHECK-LABEL: test_x86_avx_cmp_pd_256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vcmpordpd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0xc2,0xc1,0x07]
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; CHECK-NEXT: retl # encoding: [0xc3]
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%res = call <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double> %a0, <4 x double> %a1, i8 7) ; <<4 x double>> [#uses=1]
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ret <4 x double> %res
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}
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declare <4 x double> @llvm.x86.avx.cmp.pd.256(<4 x double>, <4 x double>, i8) nounwind readnone
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define <8 x float> @test_x86_avx_cmp_ps_256(<8 x float> %a0, <8 x float> %a1) {
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; CHECK-LABEL: test_x86_avx_cmp_ps_256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vcmpordps %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfc,0xc2,0xc1,0x07]
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; CHECK-NEXT: retl # encoding: [0xc3]
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%res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
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ret <8 x float> %res
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}
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define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x float> %a1) {
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; CHECK-LABEL: test_x86_avx_cmp_ps_256_pseudo_op:
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; CHECK: # BB#0:
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; CHECK-NEXT: vcmpeqps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x00]
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; CHECK-NEXT: vcmpltps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x01]
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; CHECK-NEXT: vcmpleps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x02]
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; CHECK-NEXT: vcmpunordps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x03]
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; CHECK-NEXT: vcmpneqps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x04]
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; CHECK-NEXT: vcmpnltps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x05]
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; CHECK-NEXT: vcmpnleps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x06]
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; CHECK-NEXT: vcmpordps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x07]
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; CHECK-NEXT: vcmpeq_uqps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x08]
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; CHECK-NEXT: vcmpngeps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x09]
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; CHECK-NEXT: vcmpngtps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x0a]
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; CHECK-NEXT: vcmpfalseps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x0b]
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; CHECK-NEXT: vcmpneq_oqps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x0c]
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; CHECK-NEXT: vcmpgeps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x0d]
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; CHECK-NEXT: vcmpgtps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x0e]
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; CHECK-NEXT: vcmptrueps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x0f]
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; CHECK-NEXT: vcmpeq_osps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x10]
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; CHECK-NEXT: vcmplt_oqps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x11]
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; CHECK-NEXT: vcmple_oqps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x12]
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; CHECK-NEXT: vcmpunord_sps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x13]
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; CHECK-NEXT: vcmpneq_usps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x14]
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; CHECK-NEXT: vcmpnlt_uqps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x15]
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; CHECK-NEXT: vcmpnle_uqps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x16]
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; CHECK-NEXT: vcmpord_sps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x17]
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; CHECK-NEXT: vcmpeq_usps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x18]
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; CHECK-NEXT: vcmpnge_uqps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x19]
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; CHECK-NEXT: vcmpngt_uqps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x1a]
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; CHECK-NEXT: vcmpfalse_osps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x1b]
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; CHECK-NEXT: vcmpneq_osps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x1c]
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; CHECK-NEXT: vcmpge_oqps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x1d]
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; CHECK-NEXT: vcmpgt_oqps %ymm1, %ymm0, %ymm1 # encoding: [0xc5,0xfc,0xc2,0xc9,0x1e]
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; CHECK-NEXT: vcmptrue_usps %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfc,0xc2,0xc1,0x1f]
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; CHECK-NEXT: retl # encoding: [0xc3]
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%a2 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 0) ; <<8 x float>> [#uses=1]
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%a3 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a2, i8 1) ; <<8 x float>> [#uses=1]
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%a4 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a3, i8 2) ; <<8 x float>> [#uses=1]
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%a5 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a4, i8 3) ; <<8 x float>> [#uses=1]
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%a6 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a5, i8 4) ; <<8 x float>> [#uses=1]
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%a7 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a6, i8 5) ; <<8 x float>> [#uses=1]
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%a8 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a7, i8 6) ; <<8 x float>> [#uses=1]
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%a9 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a8, i8 7) ; <<8 x float>> [#uses=1]
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%a10 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a9, i8 8) ; <<8 x float>> [#uses=1]
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%a11 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a10, i8 9) ; <<8 x float>> [#uses=1]
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%a12 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a11, i8 10) ; <<8 x float>> [#uses=1]
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%a13 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a12, i8 11) ; <<8 x float>> [#uses=1]
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%a14 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a13, i8 12) ; <<8 x float>> [#uses=1]
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%a15 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a14, i8 13) ; <<8 x float>> [#uses=1]
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%a16 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a15, i8 14) ; <<8 x float>> [#uses=1]
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%a17 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a16, i8 15) ; <<8 x float>> [#uses=1]
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%a18 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a17, i8 16) ; <<8 x float>> [#uses=1]
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%a19 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a18, i8 17) ; <<8 x float>> [#uses=1]
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%a20 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a19, i8 18) ; <<8 x float>> [#uses=1]
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%a21 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a20, i8 19) ; <<8 x float>> [#uses=1]
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%a22 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a21, i8 20) ; <<8 x float>> [#uses=1]
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%a23 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a22, i8 21) ; <<8 x float>> [#uses=1]
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%a24 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a23, i8 22) ; <<8 x float>> [#uses=1]
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%a25 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a24, i8 23) ; <<8 x float>> [#uses=1]
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%a26 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a25, i8 24) ; <<8 x float>> [#uses=1]
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%a27 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a26, i8 25) ; <<8 x float>> [#uses=1]
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%a28 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a27, i8 26) ; <<8 x float>> [#uses=1]
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%a29 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a28, i8 27) ; <<8 x float>> [#uses=1]
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%a30 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a29, i8 28) ; <<8 x float>> [#uses=1]
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%a31 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a30, i8 29) ; <<8 x float>> [#uses=1]
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%a32 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a31, i8 30) ; <<8 x float>> [#uses=1]
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%res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a32, i8 31) ; <<8 x float>> [#uses=1]
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ret <8 x float> %res
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}
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declare <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
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define <4 x float> @test_x86_avx_cvt_pd2_ps_256(<4 x double> %a0) {
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; AVX-LABEL: test_x86_avx_cvt_pd2_ps_256:
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; AVX: # BB#0:
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; AVX-NEXT: vcvtpd2ps %ymm0, %xmm0 # encoding: [0xc5,0xfd,0x5a,0xc0]
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; AVX-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
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; AVX-NEXT: retl # encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_avx_cvt_pd2_ps_256:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vcvtpd2ps %ymm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x5a,0xc0]
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; AVX512VL-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
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; AVX512VL-NEXT: retl # encoding: [0xc3]
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%res = call <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double> %a0) ; <<4 x float>> [#uses=1]
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ret <4 x float> %res
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}
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declare <4 x float> @llvm.x86.avx.cvt.pd2.ps.256(<4 x double>) nounwind readnone
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define <4 x i32> @test_x86_avx_cvt_pd2dq_256(<4 x double> %a0) {
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; AVX-LABEL: test_x86_avx_cvt_pd2dq_256:
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; AVX: # BB#0:
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; AVX-NEXT: vcvtpd2dq %ymm0, %xmm0 # encoding: [0xc5,0xff,0xe6,0xc0]
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; AVX-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
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; AVX-NEXT: retl # encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_avx_cvt_pd2dq_256:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vcvtpd2dq %ymm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xff,0xe6,0xc0]
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; AVX512VL-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
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; AVX512VL-NEXT: retl # encoding: [0xc3]
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%res = call <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1]
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ret <4 x i32> %res
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}
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declare <4 x i32> @llvm.x86.avx.cvt.pd2dq.256(<4 x double>) nounwind readnone
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define <8 x i32> @test_x86_avx_cvt_ps2dq_256(<8 x float> %a0) {
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; CHECK-LABEL: test_x86_avx_cvt_ps2dq_256:
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; CHECK: # BB#0:
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; CHECK-NEXT: vcvtps2dq %ymm0, %ymm0 # encoding: [0xc5,0xfd,0x5b,0xc0]
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; CHECK-NEXT: retl # encoding: [0xc3]
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%res = call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1]
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ret <8 x i32> %res
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}
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declare <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float>) nounwind readnone
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define <8 x float> @test_x86_avx_cvtdq2_ps_256(<8 x i32> %a0) {
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; AVX-LABEL: test_x86_avx_cvtdq2_ps_256:
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; AVX: # BB#0:
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; AVX-NEXT: vcvtdq2ps %ymm0, %ymm0 # encoding: [0xc5,0xfc,0x5b,0xc0]
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; AVX-NEXT: retl # encoding: [0xc3]
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;
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; AVX512VL-LABEL: test_x86_avx_cvtdq2_ps_256:
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; AVX512VL: # BB#0:
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; AVX512VL-NEXT: vcvtdq2ps %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x5b,0xc0]
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; AVX512VL-NEXT: retl # encoding: [0xc3]
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%res = call <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32> %a0) ; <<8 x float>> [#uses=1]
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ret <8 x float> %res
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}
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declare <8 x float> @llvm.x86.avx.cvtdq2.ps.256(<8 x i32>) nounwind readnone
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define <4 x i32> @test_x86_avx_cvtt_pd2dq_256(<4 x double> %a0) {
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; AVX-LABEL: test_x86_avx_cvtt_pd2dq_256:
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; AVX: # BB#0:
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; AVX-NEXT: vcvttpd2dq %ymm0, %xmm0 # encoding: [0xc5,0xfd,0xe6,0xc0]
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; AVX-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
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; AVX-NEXT: retl # encoding: [0xc3]
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;
|
|
; AVX512VL-LABEL: test_x86_avx_cvtt_pd2dq_256:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: vcvttpd2dq %ymm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe6,0xc0]
|
|
; AVX512VL-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%res = call <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double> %a0) ; <<4 x i32>> [#uses=1]
|
|
ret <4 x i32> %res
|
|
}
|
|
declare <4 x i32> @llvm.x86.avx.cvtt.pd2dq.256(<4 x double>) nounwind readnone
|
|
|
|
|
|
define <8 x i32> @test_x86_avx_cvtt_ps2dq_256(<8 x float> %a0) {
|
|
; AVX-LABEL: test_x86_avx_cvtt_ps2dq_256:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vcvttps2dq %ymm0, %ymm0 # encoding: [0xc5,0xfe,0x5b,0xc0]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: test_x86_avx_cvtt_ps2dq_256:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: vcvttps2dq %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfe,0x5b,0xc0]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%res = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0) ; <<8 x i32>> [#uses=1]
|
|
ret <8 x i32> %res
|
|
}
|
|
declare <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float>) nounwind readnone
|
|
|
|
|
|
define <8 x float> @test_x86_avx_dp_ps_256(<8 x float> %a0, <8 x float> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_dp_ps_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vdpps $7, %ymm1, %ymm0, %ymm0 # encoding: [0xc4,0xe3,0x7d,0x40,0xc1,0x07]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
|
|
ret <8 x float> %res
|
|
}
|
|
declare <8 x float> @llvm.x86.avx.dp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone
|
|
|
|
|
|
define <4 x double> @test_x86_avx_hadd_pd_256(<4 x double> %a0, <4 x double> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_hadd_pd_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vhaddpd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0x7c,0xc1]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
|
|
ret <4 x double> %res
|
|
}
|
|
declare <4 x double> @llvm.x86.avx.hadd.pd.256(<4 x double>, <4 x double>) nounwind readnone
|
|
|
|
|
|
define <8 x float> @test_x86_avx_hadd_ps_256(<8 x float> %a0, <8 x float> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_hadd_ps_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vhaddps %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xff,0x7c,0xc1]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
|
|
ret <8 x float> %res
|
|
}
|
|
declare <8 x float> @llvm.x86.avx.hadd.ps.256(<8 x float>, <8 x float>) nounwind readnone
|
|
|
|
|
|
define <4 x double> @test_x86_avx_hsub_pd_256(<4 x double> %a0, <4 x double> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_hsub_pd_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vhsubpd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0x7d,0xc1]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
|
|
ret <4 x double> %res
|
|
}
|
|
declare <4 x double> @llvm.x86.avx.hsub.pd.256(<4 x double>, <4 x double>) nounwind readnone
|
|
|
|
|
|
define <8 x float> @test_x86_avx_hsub_ps_256(<8 x float> %a0, <8 x float> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_hsub_ps_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vhsubps %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xff,0x7d,0xc1]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
|
|
ret <8 x float> %res
|
|
}
|
|
declare <8 x float> @llvm.x86.avx.hsub.ps.256(<8 x float>, <8 x float>) nounwind readnone
|
|
|
|
|
|
define <32 x i8> @test_x86_avx_ldu_dq_256(i8* %a0) {
|
|
; CHECK-LABEL: test_x86_avx_ldu_dq_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; CHECK-NEXT: vlddqu (%eax), %ymm0 # encoding: [0xc5,0xff,0xf0,0x00]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <32 x i8> @llvm.x86.avx.ldu.dq.256(i8* %a0) ; <<32 x i8>> [#uses=1]
|
|
ret <32 x i8> %res
|
|
}
|
|
declare <32 x i8> @llvm.x86.avx.ldu.dq.256(i8*) nounwind readonly
|
|
|
|
|
|
define <2 x double> @test_x86_avx_maskload_pd(i8* %a0, <2 x i64> %mask) {
|
|
; CHECK-LABEL: test_x86_avx_maskload_pd:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; CHECK-NEXT: vmaskmovpd (%eax), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x2d,0x00]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <2 x double> @llvm.x86.avx.maskload.pd(i8* %a0, <2 x i64> %mask) ; <<2 x double>> [#uses=1]
|
|
ret <2 x double> %res
|
|
}
|
|
declare <2 x double> @llvm.x86.avx.maskload.pd(i8*, <2 x i64>) nounwind readonly
|
|
|
|
|
|
define <4 x double> @test_x86_avx_maskload_pd_256(i8* %a0, <4 x i64> %mask) {
|
|
; CHECK-LABEL: test_x86_avx_maskload_pd_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; CHECK-NEXT: vmaskmovpd (%eax), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x2d,0x00]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <4 x double> @llvm.x86.avx.maskload.pd.256(i8* %a0, <4 x i64> %mask) ; <<4 x double>> [#uses=1]
|
|
ret <4 x double> %res
|
|
}
|
|
declare <4 x double> @llvm.x86.avx.maskload.pd.256(i8*, <4 x i64>) nounwind readonly
|
|
|
|
|
|
define <4 x float> @test_x86_avx_maskload_ps(i8* %a0, <4 x i32> %mask) {
|
|
; CHECK-LABEL: test_x86_avx_maskload_ps:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; CHECK-NEXT: vmaskmovps (%eax), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x2c,0x00]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <4 x float> @llvm.x86.avx.maskload.ps(i8* %a0, <4 x i32> %mask) ; <<4 x float>> [#uses=1]
|
|
ret <4 x float> %res
|
|
}
|
|
declare <4 x float> @llvm.x86.avx.maskload.ps(i8*, <4 x i32>) nounwind readonly
|
|
|
|
|
|
define <8 x float> @test_x86_avx_maskload_ps_256(i8* %a0, <8 x i32> %mask) {
|
|
; CHECK-LABEL: test_x86_avx_maskload_ps_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; CHECK-NEXT: vmaskmovps (%eax), %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x2c,0x00]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <8 x float> @llvm.x86.avx.maskload.ps.256(i8* %a0, <8 x i32> %mask) ; <<8 x float>> [#uses=1]
|
|
ret <8 x float> %res
|
|
}
|
|
declare <8 x float> @llvm.x86.avx.maskload.ps.256(i8*, <8 x i32>) nounwind readonly
|
|
|
|
|
|
define void @test_x86_avx_maskstore_pd(i8* %a0, <2 x i64> %mask, <2 x double> %a2) {
|
|
; CHECK-LABEL: test_x86_avx_maskstore_pd:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; CHECK-NEXT: vmaskmovpd %xmm1, %xmm0, (%eax) # encoding: [0xc4,0xe2,0x79,0x2f,0x08]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
call void @llvm.x86.avx.maskstore.pd(i8* %a0, <2 x i64> %mask, <2 x double> %a2)
|
|
ret void
|
|
}
|
|
declare void @llvm.x86.avx.maskstore.pd(i8*, <2 x i64>, <2 x double>) nounwind
|
|
|
|
|
|
define void @test_x86_avx_maskstore_pd_256(i8* %a0, <4 x i64> %mask, <4 x double> %a2) {
|
|
; CHECK-LABEL: test_x86_avx_maskstore_pd_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; CHECK-NEXT: vmaskmovpd %ymm1, %ymm0, (%eax) # encoding: [0xc4,0xe2,0x7d,0x2f,0x08]
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
call void @llvm.x86.avx.maskstore.pd.256(i8* %a0, <4 x i64> %mask, <4 x double> %a2)
|
|
ret void
|
|
}
|
|
declare void @llvm.x86.avx.maskstore.pd.256(i8*, <4 x i64>, <4 x double>) nounwind
|
|
|
|
|
|
define void @test_x86_avx_maskstore_ps(i8* %a0, <4 x i32> %mask, <4 x float> %a2) {
|
|
; CHECK-LABEL: test_x86_avx_maskstore_ps:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; CHECK-NEXT: vmaskmovps %xmm1, %xmm0, (%eax) # encoding: [0xc4,0xe2,0x79,0x2e,0x08]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
call void @llvm.x86.avx.maskstore.ps(i8* %a0, <4 x i32> %mask, <4 x float> %a2)
|
|
ret void
|
|
}
|
|
declare void @llvm.x86.avx.maskstore.ps(i8*, <4 x i32>, <4 x float>) nounwind
|
|
|
|
|
|
define void @test_x86_avx_maskstore_ps_256(i8* %a0, <8 x i32> %mask, <8 x float> %a2) {
|
|
; CHECK-LABEL: test_x86_avx_maskstore_ps_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; CHECK-NEXT: vmaskmovps %ymm1, %ymm0, (%eax) # encoding: [0xc4,0xe2,0x7d,0x2e,0x08]
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
call void @llvm.x86.avx.maskstore.ps.256(i8* %a0, <8 x i32> %mask, <8 x float> %a2)
|
|
ret void
|
|
}
|
|
declare void @llvm.x86.avx.maskstore.ps.256(i8*, <8 x i32>, <8 x float>) nounwind
|
|
|
|
|
|
define <4 x double> @test_x86_avx_max_pd_256(<4 x double> %a0, <4 x double> %a1) {
|
|
; AVX-LABEL: test_x86_avx_max_pd_256:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0x5f,0xc1]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: test_x86_avx_max_pd_256:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: vmaxpd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x5f,0xc1]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%res = call <4 x double> @llvm.x86.avx.max.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
|
|
ret <4 x double> %res
|
|
}
|
|
declare <4 x double> @llvm.x86.avx.max.pd.256(<4 x double>, <4 x double>) nounwind readnone
|
|
|
|
|
|
define <8 x float> @test_x86_avx_max_ps_256(<8 x float> %a0, <8 x float> %a1) {
|
|
; AVX-LABEL: test_x86_avx_max_ps_256:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vmaxps %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfc,0x5f,0xc1]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: test_x86_avx_max_ps_256:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: vmaxps %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x5f,0xc1]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%res = call <8 x float> @llvm.x86.avx.max.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
|
|
ret <8 x float> %res
|
|
}
|
|
declare <8 x float> @llvm.x86.avx.max.ps.256(<8 x float>, <8 x float>) nounwind readnone
|
|
|
|
|
|
define <4 x double> @test_x86_avx_min_pd_256(<4 x double> %a0, <4 x double> %a1) {
|
|
; AVX-LABEL: test_x86_avx_min_pd_256:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vminpd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0x5d,0xc1]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: test_x86_avx_min_pd_256:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: vminpd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x5d,0xc1]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%res = call <4 x double> @llvm.x86.avx.min.pd.256(<4 x double> %a0, <4 x double> %a1) ; <<4 x double>> [#uses=1]
|
|
ret <4 x double> %res
|
|
}
|
|
declare <4 x double> @llvm.x86.avx.min.pd.256(<4 x double>, <4 x double>) nounwind readnone
|
|
|
|
|
|
define <8 x float> @test_x86_avx_min_ps_256(<8 x float> %a0, <8 x float> %a1) {
|
|
; AVX-LABEL: test_x86_avx_min_ps_256:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vminps %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfc,0x5d,0xc1]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: test_x86_avx_min_ps_256:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: vminps %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x5d,0xc1]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%res = call <8 x float> @llvm.x86.avx.min.ps.256(<8 x float> %a0, <8 x float> %a1) ; <<8 x float>> [#uses=1]
|
|
ret <8 x float> %res
|
|
}
|
|
declare <8 x float> @llvm.x86.avx.min.ps.256(<8 x float>, <8 x float>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_movmsk_pd_256(<4 x double> %a0) {
|
|
; CHECK-LABEL: test_x86_avx_movmsk_pd_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vmovmskpd %ymm0, %eax # encoding: [0xc5,0xfd,0x50,0xc0]
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %a0) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_movmsk_ps_256(<8 x float> %a0) {
|
|
; CHECK-LABEL: test_x86_avx_movmsk_ps_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vmovmskps %ymm0, %eax # encoding: [0xc5,0xfc,0x50,0xc0]
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %a0) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) nounwind readnone
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
define i32 @test_x86_avx_ptestc_256(<4 x i64> %a0, <4 x i64> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_ptestc_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vptest %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x17,0xc1]
|
|
; CHECK-NEXT: setb %al # encoding: [0x0f,0x92,0xc0]
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.ptestc.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.ptestc.256(<4 x i64>, <4 x i64>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_ptestnzc_256(<4 x i64> %a0, <4 x i64> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_ptestnzc_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vptest %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x17,0xc1]
|
|
; CHECK-NEXT: seta %al # encoding: [0x0f,0x97,0xc0]
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.ptestnzc.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.ptestnzc.256(<4 x i64>, <4 x i64>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_ptestz_256(<4 x i64> %a0, <4 x i64> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_ptestz_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vptest %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x17,0xc1]
|
|
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.ptestz.256(<4 x i64> %a0, <4 x i64> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.ptestz.256(<4 x i64>, <4 x i64>) nounwind readnone
|
|
|
|
|
|
define <8 x float> @test_x86_avx_rcp_ps_256(<8 x float> %a0) {
|
|
; AVX-LABEL: test_x86_avx_rcp_ps_256:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vrcpps %ymm0, %ymm0 # encoding: [0xc5,0xfc,0x53,0xc0]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: test_x86_avx_rcp_ps_256:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: vrcp14ps %ymm0, %ymm0 # encoding: [0x62,0xf2,0x7d,0x28,0x4c,0xc0]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%res = call <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
|
|
ret <8 x float> %res
|
|
}
|
|
declare <8 x float> @llvm.x86.avx.rcp.ps.256(<8 x float>) nounwind readnone
|
|
|
|
|
|
define <4 x double> @test_x86_avx_round_pd_256(<4 x double> %a0) {
|
|
; CHECK-LABEL: test_x86_avx_round_pd_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vroundpd $7, %ymm0, %ymm0 # encoding: [0xc4,0xe3,0x7d,0x09,0xc0,0x07]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <4 x double> @llvm.x86.avx.round.pd.256(<4 x double> %a0, i32 7) ; <<4 x double>> [#uses=1]
|
|
ret <4 x double> %res
|
|
}
|
|
declare <4 x double> @llvm.x86.avx.round.pd.256(<4 x double>, i32) nounwind readnone
|
|
|
|
|
|
define <8 x float> @test_x86_avx_round_ps_256(<8 x float> %a0) {
|
|
; CHECK-LABEL: test_x86_avx_round_ps_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vroundps $7, %ymm0, %ymm0 # encoding: [0xc4,0xe3,0x7d,0x08,0xc0,0x07]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <8 x float> @llvm.x86.avx.round.ps.256(<8 x float> %a0, i32 7) ; <<8 x float>> [#uses=1]
|
|
ret <8 x float> %res
|
|
}
|
|
declare <8 x float> @llvm.x86.avx.round.ps.256(<8 x float>, i32) nounwind readnone
|
|
|
|
|
|
define <8 x float> @test_x86_avx_rsqrt_ps_256(<8 x float> %a0) {
|
|
; AVX-LABEL: test_x86_avx_rsqrt_ps_256:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vrsqrtps %ymm0, %ymm0 # encoding: [0xc5,0xfc,0x52,0xc0]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: test_x86_avx_rsqrt_ps_256:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: vrsqrt14ps %ymm0, %ymm0 # encoding: [0x62,0xf2,0x7d,0x28,0x4e,0xc0]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%res = call <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
|
|
ret <8 x float> %res
|
|
}
|
|
declare <8 x float> @llvm.x86.avx.rsqrt.ps.256(<8 x float>) nounwind readnone
|
|
|
|
|
|
define <4 x double> @test_x86_avx_sqrt_pd_256(<4 x double> %a0) {
|
|
; CHECK-LABEL: test_x86_avx_sqrt_pd_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vsqrtpd %ymm0, %ymm0 # encoding: [0xc5,0xfd,0x51,0xc0]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double> %a0) ; <<4 x double>> [#uses=1]
|
|
ret <4 x double> %res
|
|
}
|
|
declare <4 x double> @llvm.x86.avx.sqrt.pd.256(<4 x double>) nounwind readnone
|
|
|
|
|
|
define <8 x float> @test_x86_avx_sqrt_ps_256(<8 x float> %a0) {
|
|
; CHECK-LABEL: test_x86_avx_sqrt_ps_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vsqrtps %ymm0, %ymm0 # encoding: [0xc5,0xfc,0x51,0xc0]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float> %a0) ; <<8 x float>> [#uses=1]
|
|
ret <8 x float> %res
|
|
}
|
|
declare <8 x float> @llvm.x86.avx.sqrt.ps.256(<8 x float>) nounwind readnone
|
|
|
|
|
|
define <2 x double> @test_x86_avx_vpermilvar_pd(<2 x double> %a0, <2 x i64> %a1) {
|
|
; AVX-LABEL: test_x86_avx_vpermilvar_pd:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpermilpd %xmm1, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x0d,0xc1]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: test_x86_avx_vpermilvar_pd:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: vpermilpd %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x0d,0xc1]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%res = call <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double> %a0, <2 x i64> %a1) ; <<2 x double>> [#uses=1]
|
|
ret <2 x double> %res
|
|
}
|
|
declare <2 x double> @llvm.x86.avx.vpermilvar.pd(<2 x double>, <2 x i64>) nounwind readnone
|
|
|
|
|
|
define <4 x double> @test_x86_avx_vpermilvar_pd_256(<4 x double> %a0, <4 x i64> %a1) {
|
|
; AVX-LABEL: test_x86_avx_vpermilvar_pd_256:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpermilpd %ymm1, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x0d,0xc1]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: test_x86_avx_vpermilvar_pd_256:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: vpermilpd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x0d,0xc1]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%res = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> %a1) ; <<4 x double>> [#uses=1]
|
|
ret <4 x double> %res
|
|
}
|
|
declare <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double>, <4 x i64>) nounwind readnone
|
|
|
|
define <4 x double> @test_x86_avx_vpermilvar_pd_256_2(<4 x double> %a0) {
|
|
; AVX-LABEL: test_x86_avx_vpermilvar_pd_256_2:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpermilpd $9, %ymm0, %ymm0 # encoding: [0xc4,0xe3,0x7d,0x05,0xc0,0x09]
|
|
; AVX-NEXT: # ymm0 = ymm0[1,0,2,3]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: test_x86_avx_vpermilvar_pd_256_2:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: vpermilpd $9, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x05,0xc0,0x09]
|
|
; AVX512VL-NEXT: # ymm0 = ymm0[1,0,2,3]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%res = call <4 x double> @llvm.x86.avx.vpermilvar.pd.256(<4 x double> %a0, <4 x i64> <i64 2, i64 0, i64 0, i64 2>) ; <<4 x double>> [#uses=1]
|
|
ret <4 x double> %res
|
|
}
|
|
|
|
define <4 x float> @test_x86_avx_vpermilvar_ps(<4 x float> %a0, <4 x i32> %a1) {
|
|
; AVX-LABEL: test_x86_avx_vpermilvar_ps:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpermilps %xmm1, %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x0c,0xc1]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: test_x86_avx_vpermilvar_ps:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: vpermilps %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x0c,0xc1]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a1) ; <<4 x float>> [#uses=1]
|
|
ret <4 x float> %res
|
|
}
|
|
define <4 x float> @test_x86_avx_vpermilvar_ps_load(<4 x float> %a0, <4 x i32>* %a1) {
|
|
; AVX-LABEL: test_x86_avx_vpermilvar_ps_load:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; AVX-NEXT: vpermilps (%eax), %xmm0, %xmm0 # encoding: [0xc4,0xe2,0x79,0x0c,0x00]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: test_x86_avx_vpermilvar_ps_load:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; AVX512VL-NEXT: vpermilps (%eax), %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x79,0x0c,0x00]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%a2 = load <4 x i32>, <4 x i32>* %a1
|
|
%res = call <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float> %a0, <4 x i32> %a2) ; <<4 x float>> [#uses=1]
|
|
ret <4 x float> %res
|
|
}
|
|
declare <4 x float> @llvm.x86.avx.vpermilvar.ps(<4 x float>, <4 x i32>) nounwind readnone
|
|
|
|
|
|
define <8 x float> @test_x86_avx_vpermilvar_ps_256(<8 x float> %a0, <8 x i32> %a1) {
|
|
; AVX-LABEL: test_x86_avx_vpermilvar_ps_256:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: vpermilps %ymm1, %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x0c,0xc1]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: test_x86_avx_vpermilvar_ps_256:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: vpermilps %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7d,0x0c,0xc1]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%res = call <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float> %a0, <8 x i32> %a1) ; <<8 x float>> [#uses=1]
|
|
ret <8 x float> %res
|
|
}
|
|
declare <8 x float> @llvm.x86.avx.vpermilvar.ps.256(<8 x float>, <8 x i32>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_vtestc_pd(<2 x double> %a0, <2 x double> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_vtestc_pd:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vtestpd %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x79,0x0f,0xc1]
|
|
; CHECK-NEXT: setb %al # encoding: [0x0f,0x92,0xc0]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.vtestc.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.vtestc.pd(<2 x double>, <2 x double>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_vtestc_pd_256(<4 x double> %a0, <4 x double> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_vtestc_pd_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vtestpd %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x0f,0xc1]
|
|
; CHECK-NEXT: setb %al # encoding: [0x0f,0x92,0xc0]
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.vtestc.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.vtestc.pd.256(<4 x double>, <4 x double>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_vtestc_ps(<4 x float> %a0, <4 x float> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_vtestc_ps:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vtestps %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x79,0x0e,0xc1]
|
|
; CHECK-NEXT: setb %al # encoding: [0x0f,0x92,0xc0]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.vtestc.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.vtestc.ps(<4 x float>, <4 x float>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_vtestc_ps_256(<8 x float> %a0, <8 x float> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_vtestc_ps_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vtestps %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x0e,0xc1]
|
|
; CHECK-NEXT: setb %al # encoding: [0x0f,0x92,0xc0]
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.vtestc.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.vtestc.ps.256(<8 x float>, <8 x float>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_vtestnzc_pd(<2 x double> %a0, <2 x double> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_vtestnzc_pd:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vtestpd %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x79,0x0f,0xc1]
|
|
; CHECK-NEXT: seta %al # encoding: [0x0f,0x97,0xc0]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.vtestnzc.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.vtestnzc.pd(<2 x double>, <2 x double>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_vtestnzc_pd_256(<4 x double> %a0, <4 x double> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_vtestnzc_pd_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vtestpd %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x0f,0xc1]
|
|
; CHECK-NEXT: seta %al # encoding: [0x0f,0x97,0xc0]
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.vtestnzc.pd.256(<4 x double>, <4 x double>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_vtestnzc_ps(<4 x float> %a0, <4 x float> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_vtestnzc_ps:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vtestps %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x79,0x0e,0xc1]
|
|
; CHECK-NEXT: seta %al # encoding: [0x0f,0x97,0xc0]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.vtestnzc.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.vtestnzc.ps(<4 x float>, <4 x float>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_vtestnzc_ps_256(<8 x float> %a0, <8 x float> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_vtestnzc_ps_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vtestps %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x0e,0xc1]
|
|
; CHECK-NEXT: seta %al # encoding: [0x0f,0x97,0xc0]
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.vtestnzc.ps.256(<8 x float>, <8 x float>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_vtestz_pd(<2 x double> %a0, <2 x double> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_vtestz_pd:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vtestpd %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x79,0x0f,0xc1]
|
|
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.vtestz.pd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.vtestz.pd(<2 x double>, <2 x double>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_vtestz_pd_256(<4 x double> %a0, <4 x double> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_vtestz_pd_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vtestpd %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x0f,0xc1]
|
|
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.vtestz.pd.256(<4 x double> %a0, <4 x double> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.vtestz.pd.256(<4 x double>, <4 x double>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_vtestz_ps(<4 x float> %a0, <4 x float> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_vtestz_ps:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vtestps %xmm1, %xmm0 # encoding: [0xc4,0xe2,0x79,0x0e,0xc1]
|
|
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.vtestz.ps(<4 x float> %a0, <4 x float> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.vtestz.ps(<4 x float>, <4 x float>) nounwind readnone
|
|
|
|
|
|
define i32 @test_x86_avx_vtestz_ps_256(<8 x float> %a0, <8 x float> %a1) {
|
|
; CHECK-LABEL: test_x86_avx_vtestz_ps_256:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0]
|
|
; CHECK-NEXT: vtestps %ymm1, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x0e,0xc1]
|
|
; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0]
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call i32 @llvm.x86.avx.vtestz.ps.256(<8 x float> %a0, <8 x float> %a1) ; <i32> [#uses=1]
|
|
ret i32 %res
|
|
}
|
|
declare i32 @llvm.x86.avx.vtestz.ps.256(<8 x float>, <8 x float>) nounwind readnone
|
|
|
|
|
|
define void @test_x86_avx_vzeroall() {
|
|
; CHECK-LABEL: test_x86_avx_vzeroall:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vzeroall # encoding: [0xc5,0xfc,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
call void @llvm.x86.avx.vzeroall()
|
|
ret void
|
|
}
|
|
declare void @llvm.x86.avx.vzeroall() nounwind
|
|
|
|
|
|
define void @test_x86_avx_vzeroupper() {
|
|
; CHECK-LABEL: test_x86_avx_vzeroupper:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
call void @llvm.x86.avx.vzeroupper()
|
|
ret void
|
|
}
|
|
declare void @llvm.x86.avx.vzeroupper() nounwind
|
|
|
|
define void @movnt_dq(i8* %p, <2 x i64> %a1) nounwind {
|
|
; AVX-LABEL: movnt_dq:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; AVX-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x76,0xc9]
|
|
; AVX-NEXT: vpsubq %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfb,0xc1]
|
|
; AVX-NEXT: vmovntdq %ymm0, (%eax) # encoding: [0xc5,0xfd,0xe7,0x00]
|
|
; AVX-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: movnt_dq:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; AVX512VL-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x76,0xc9]
|
|
; AVX512VL-NEXT: vpsubq %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xfb,0xc1]
|
|
; AVX512VL-NEXT: vmovntdq %ymm0, (%eax) # EVEX TO VEX Compression encoding: [0xc5,0xfd,0xe7,0x00]
|
|
; AVX512VL-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%a2 = add <2 x i64> %a1, <i64 1, i64 1>
|
|
%a3 = shufflevector <2 x i64> %a2, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
|
|
tail call void @llvm.x86.avx.movnt.dq.256(i8* %p, <4 x i64> %a3) nounwind
|
|
ret void
|
|
}
|
|
declare void @llvm.x86.avx.movnt.dq.256(i8*, <4 x i64>) nounwind
|
|
|
|
define void @movnt_ps(i8* %p, <8 x float> %a) nounwind {
|
|
; AVX-LABEL: movnt_ps:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; AVX-NEXT: vmovntps %ymm0, (%eax) # encoding: [0xc5,0xfc,0x2b,0x00]
|
|
; AVX-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: movnt_ps:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; AVX512VL-NEXT: vmovntps %ymm0, (%eax) # EVEX TO VEX Compression encoding: [0xc5,0xfc,0x2b,0x00]
|
|
; AVX512VL-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
tail call void @llvm.x86.avx.movnt.ps.256(i8* %p, <8 x float> %a) nounwind
|
|
ret void
|
|
}
|
|
declare void @llvm.x86.avx.movnt.ps.256(i8*, <8 x float>) nounwind
|
|
|
|
define void @movnt_pd(i8* %p, <4 x double> %a1) nounwind {
|
|
; add operation forces the execution domain.
|
|
; AVX-LABEL: movnt_pd:
|
|
; AVX: # BB#0:
|
|
; AVX-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; AVX-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # encoding: [0xc5,0xf1,0x57,0xc9]
|
|
; AVX-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # encoding: [0xc5,0xfd,0x58,0xc1]
|
|
; AVX-NEXT: vmovntpd %ymm0, (%eax) # encoding: [0xc5,0xfd,0x2b,0x00]
|
|
; AVX-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; AVX-NEXT: retl # encoding: [0xc3]
|
|
;
|
|
; AVX512VL-LABEL: movnt_pd:
|
|
; AVX512VL: # BB#0:
|
|
; AVX512VL-NEXT: movl {{[0-9]+}}(%esp), %eax # encoding: [0x8b,0x44,0x24,0x04]
|
|
; AVX512VL-NEXT: vxorpd %xmm1, %xmm1, %xmm1 # EVEX TO VEX Compression encoding: [0xc5,0xf1,0x57,0xc9]
|
|
; AVX512VL-NEXT: vaddpd %ymm1, %ymm0, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x58,0xc1]
|
|
; AVX512VL-NEXT: vmovntpd %ymm0, (%eax) # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x2b,0x00]
|
|
; AVX512VL-NEXT: vzeroupper # encoding: [0xc5,0xf8,0x77]
|
|
; AVX512VL-NEXT: retl # encoding: [0xc3]
|
|
%a2 = fadd <4 x double> %a1, <double 0x0, double 0x0, double 0x0, double 0x0>
|
|
tail call void @llvm.x86.avx.movnt.pd.256(i8* %p, <4 x double> %a2) nounwind
|
|
ret void
|
|
}
|
|
declare void @llvm.x86.avx.movnt.pd.256(i8*, <4 x double>) nounwind
|
|
|
|
|
|
; Check for pclmulqdq
|
|
define <2 x i64> @test_x86_pclmulqdq(<2 x i64> %a0, <2 x i64> %a1) {
|
|
; CHECK-LABEL: test_x86_pclmulqdq:
|
|
; CHECK: # BB#0:
|
|
; CHECK-NEXT: vpclmulqdq $0, %xmm1, %xmm0, %xmm0 # encoding: [0xc4,0xe3,0x79,0x44,0xc1,0x00]
|
|
; CHECK-NEXT: retl # encoding: [0xc3]
|
|
%res = call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a0, <2 x i64> %a1, i8 0) ; <<2 x i64>> [#uses=1]
|
|
ret <2 x i64> %res
|
|
}
|
|
declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8) nounwind readnone
|