llvm-project/llvm/test/CodeGen
Jay Foad 6eb5b06ecf [AMDGPU] Regenerate checks to fix prefixes broken in D96340. NFC. 2021-04-06 11:43:53 +01:00
..
AArch64 [test, AArch64] Fix use of var defined in CHECK-NOT 2021-04-06 10:45:08 +01:00
AMDGPU [AMDGPU] Regenerate checks to fix prefixes broken in D96340. NFC. 2021-04-06 11:43:53 +01:00
ARC
ARM Support {S,U}REMEqFold before legalization 2021-04-01 01:35:41 +03:00
AVR [AVR] Fix lifeness issues in the AVR backend 2021-03-04 14:04:39 +01:00
BPF BPF: add extern func to data sections if specified 2021-03-25 16:03:29 -07:00
Generic Re-apply "[lli] Make -jit-kind=orc the default JIT engine" 2021-03-30 12:08:26 +02:00
Hexagon [Hexagon, test] Fix use of undef FileCheck var 2021-04-02 18:47:49 +01:00
Inputs
Lanai
M68k [DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling 2021-03-19 16:02:31 +00:00
MIR MIR: Fix missing serialization for HasTailCall 2021-03-21 13:14:04 -04:00
MSP430
Mips [MIPS, test] Fix use of undef FileCheck var 2021-04-02 00:59:49 +01:00
NVPTX [NVPTX] CUDA does provide malloc/free since compute capability 2.X 2021-03-15 22:45:56 -05:00
PowerPC [PPC] Regenerate PR27078 test checks 2021-04-01 18:11:46 +01:00
RISCV [RISCV] When custom iseling masked stores, copy the mask into V0 instead of virtual register. 2021-04-05 21:28:32 -07:00
SPARC [LegalizeTypes] Improve ExpandIntRes_XMULO codegen. 2021-03-01 09:54:32 -08:00
SystemZ [SystemZ] Reimplement the i8/i16 compare-and-swap logic. 2021-03-03 14:04:32 -06:00
Thumb Support {S,U}REMEqFold before legalization 2021-04-01 01:35:41 +03:00
Thumb2 Support {S,U}REMEqFold before legalization 2021-04-01 01:35:41 +03:00
VE [test] Fix CodeGen/VE/Scalar tests 2021-03-02 15:30:44 -08:00
WebAssembly [NFC][WebAssembly] Removed mangled name from test. 2021-04-06 08:55:27 +01:00
WinCFGuard
WinEH
X86 [X86] Fold xor(zext(xor(x,c1)),c2) -> xor(zext(x),xor(zext(c1),c2)) 2021-04-05 11:40:37 +01:00
XCore [CodeGen] Report a normal instead of fatal error for label redefinition 2021-03-09 10:54:41 +00:00