forked from OSchip/llvm-project
110 lines
4.0 KiB
YAML
110 lines
4.0 KiB
YAML
# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-wqm -o - %s | FileCheck %s
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---
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# Check for awareness that s_or_saveexec_b64 clobbers SCC
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#
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#CHECK: ENTER_WWM
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#CHECK: S_CMP_LT_I32
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#CHECK: S_CSELECT_B32
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name: test_wwm_scc
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: sgpr_32, preferred-register: '' }
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- { id: 1, class: sgpr_32, preferred-register: '' }
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- { id: 2, class: sgpr_32, preferred-register: '' }
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- { id: 3, class: vgpr_32, preferred-register: '' }
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- { id: 4, class: vgpr_32, preferred-register: '' }
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- { id: 5, class: sgpr_32, preferred-register: '' }
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- { id: 6, class: vgpr_32, preferred-register: '' }
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- { id: 7, class: vgpr_32, preferred-register: '' }
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- { id: 8, class: sreg_32_xm0, preferred-register: '' }
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- { id: 9, class: sreg_32, preferred-register: '' }
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- { id: 10, class: sreg_32, preferred-register: '' }
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- { id: 11, class: vgpr_32, preferred-register: '' }
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- { id: 12, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$sgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr1', virtual-reg: '%1' }
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- { reg: '$sgpr2', virtual-reg: '%2' }
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- { reg: '$vgpr0', virtual-reg: '%3' }
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0
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%3 = COPY $vgpr0
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%2 = COPY $sgpr2
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%1 = COPY $sgpr1
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%0 = COPY $sgpr0
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S_CMP_LT_I32 0, %0, implicit-def $scc
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%12 = V_ADD_I32_e32 %3, %3, implicit-def $vcc, implicit $exec
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%5 = S_CSELECT_B32 %2, %1, implicit $scc
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%11 = V_ADD_I32_e32 %5, %12, implicit-def $vcc, implicit $exec
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$vgpr0 = WWM %11, implicit $exec
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SI_RETURN_TO_EPILOG $vgpr0
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...
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---
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# V_SET_INACTIVE, when its second operand is undef, is replaced by a
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# COPY by si-wqm. Ensure the instruction is removed.
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#CHECK-NOT: V_SET_INACTIVE
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name: no_cfg
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alignment: 1
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers:
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- { id: 0, class: sgpr_32, preferred-register: '' }
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- { id: 1, class: sgpr_32, preferred-register: '' }
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- { id: 2, class: sgpr_32, preferred-register: '' }
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- { id: 3, class: sgpr_32, preferred-register: '' }
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- { id: 4, class: sgpr_32, preferred-register: '' }
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- { id: 5, class: sgpr_128, preferred-register: '' }
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- { id: 6, class: sgpr_128, preferred-register: '' }
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- { id: 7, class: sreg_32, preferred-register: '' }
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- { id: 8, class: vreg_64, preferred-register: '' }
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- { id: 9, class: sreg_32, preferred-register: '' }
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- { id: 10, class: vgpr_32, preferred-register: '' }
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- { id: 11, class: vgpr_32, preferred-register: '' }
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- { id: 12, class: sreg_32, preferred-register: '' }
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- { id: 13, class: vgpr_32, preferred-register: '' }
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- { id: 14, class: vgpr_32, preferred-register: '' }
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- { id: 15, class: vgpr_32, preferred-register: '' }
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- { id: 16, class: vgpr_32, preferred-register: '' }
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liveins:
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- { reg: '$sgpr0', virtual-reg: '%0' }
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- { reg: '$sgpr1', virtual-reg: '%1' }
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- { reg: '$sgpr2', virtual-reg: '%2' }
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- { reg: '$sgpr3', virtual-reg: '%3' }
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
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%3:sgpr_32 = COPY $sgpr3
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%2:sgpr_32 = COPY $sgpr2
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%1:sgpr_32 = COPY $sgpr1
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%0:sgpr_32 = COPY $sgpr0
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%6:sgpr_128 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2, %3, %subreg.sub3
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%5:sgpr_128 = COPY %6
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%7:sreg_32 = S_MOV_B32 0
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%8:vreg_64 = BUFFER_LOAD_DWORDX2_OFFSET %6, %7, 0, 0, 0, 0, 0, 0, implicit $exec
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%16:vgpr_32 = COPY %8.sub1
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%11:vgpr_32 = COPY %16
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%10:vgpr_32 = V_SET_INACTIVE_B32 %11, undef %12:sreg_32, implicit $exec
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%14:vgpr_32 = COPY %7
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%13:vgpr_32 = V_MOV_B32_dpp %14, killed %10, 323, 12, 15, 0, implicit $exec
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early-clobber %15:vgpr_32 = WWM killed %13, implicit $exec
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BUFFER_STORE_DWORD_OFFSET_exact killed %15, %6, %7, 4, 0, 0, 0, 0, 0, implicit $exec
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S_ENDPGM 0
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...
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