forked from OSchip/llvm-project
143 lines
4.8 KiB
C++
143 lines
4.8 KiB
C++
//===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8TargetMachine.h"
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#include "SparcV8.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetMachineImpls.h"
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#include "llvm/Target/TargetMachineRegistry.h"
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#include "llvm/Transforms/Scalar.h"
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#include <iostream>
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using namespace llvm;
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namespace {
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// Register the target.
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RegisterTarget<SparcV8TargetMachine> X("sparcv8", "SPARC V8 (experimental)");
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}
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// allocateSparcV8TargetMachine - Allocate and return a subclass of
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// TargetMachine that implements the SparcV8 backend.
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//
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TargetMachine *llvm::allocateSparcV8TargetMachine(const Module &M,
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IntrinsicLowering *IL) {
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return new SparcV8TargetMachine(M, IL);
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}
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/// SparcV8TargetMachine ctor - Create an ILP32 architecture model
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///
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SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
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IntrinsicLowering *IL)
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: TargetMachine("SparcV8", IL, true, 4, 4, 4, 4, 4),
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FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), JITInfo(*this) {
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}
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/// addPassesToEmitAssembly - Add passes to the specified pass manager
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/// to implement a static compiler for this target.
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///
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bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM,
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std::ostream &Out) {
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// Replace malloc and free instructions with library calls.
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PM.add(createLowerAllocationsPass());
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// FIXME: implement the select instruction in the instruction selector.
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PM.add(createLowerSelectPass());
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// FIXME: implement the switch instruction in the instruction selector.
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PM.add(createLowerSwitchPass());
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// FIXME: implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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PM.add(createLowerConstantExpressionsPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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PM.add(createSparcV8SimpleInstructionSelector(*this));
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// Print machine instructions as they were initially generated.
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createRegisterAllocator());
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PM.add(createPrologEpilogCodeInserter());
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// Print machine instructions after register allocation and prolog/epilog
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// insertion.
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createSparcV8DelaySlotFillerPass(*this));
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// Print machine instructions after filling delay slots.
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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// Output assembly language.
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PM.add(createSparcV8CodePrinterPass(Out, *this));
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// Delete the MachineInstrs we generated, since they're no longer needed.
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PM.add(createMachineCodeDeleter());
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return false;
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}
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/// addPassesToJITCompile - Add passes to the specified pass manager to
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/// implement a fast dynamic compiler for this target.
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///
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void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
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// FIXME: Implement efficient support for garbage collection intrinsics.
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PM.add(createLowerGCPass());
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// Replace malloc and free instructions with library calls.
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PM.add(createLowerAllocationsPass());
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// FIXME: implement the select instruction in the instruction selector.
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PM.add(createLowerSelectPass());
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// FIXME: implement the switch instruction in the instruction selector.
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PM.add(createLowerSwitchPass());
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// FIXME: implement the invoke/unwind instructions!
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PM.add(createLowerInvokePass());
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PM.add(createLowerConstantExpressionsPass());
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// Make sure that no unreachable blocks are instruction selected.
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PM.add(createUnreachableBlockEliminationPass());
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PM.add(createSparcV8SimpleInstructionSelector(TM));
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// Print machine instructions as they were initially generated.
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createRegisterAllocator());
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PM.add(createPrologEpilogCodeInserter());
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// Print machine instructions after register allocation and prolog/epilog
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// insertion.
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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PM.add(createSparcV8DelaySlotFillerPass(TM));
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// Print machine instructions after filling delay slots.
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if (PrintMachineCode)
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PM.add(createMachineFunctionPrinterPass(&std::cerr));
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}
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