llvm-project/llvm/lib/Target/Alpha
Evan Cheng 5d9fd977d3 Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.

llvm-svn: 30714
2006-10-04 00:56:09 +00:00
..
.cvsignore ignore generated files 2005-09-07 23:47:44 +00:00
Alpha.h A pass to remove the worst of the replay trap offenders, and as a bonus, align basic blocks when it is free to do so 2006-09-18 19:44:29 +00:00
Alpha.td getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
AlphaAsmPrinter.cpp Jump tables on Alpha 2006-09-18 18:01:03 +00:00
AlphaCodeEmitter.cpp Resolve BB references with relocation. 2006-07-27 18:21:10 +00:00
AlphaISelDAGToDAG.cpp Do not use getTargetNode() and SelectNodeTo() which takes more than 3 2006-08-27 08:14:06 +00:00
AlphaISelLowering.cpp Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an 2006-10-04 00:56:09 +00:00
AlphaISelLowering.h inline asm, at least for floats 2006-06-21 13:37:27 +00:00
AlphaInstrFormats.td Let the alpha breakage begin. First Formals and RET. next Calls 2006-06-12 18:09:24 +00:00
AlphaInstrInfo.cpp these are copies too 2006-03-09 18:18:51 +00:00
AlphaInstrInfo.h isStoreToStackSlot 2006-02-03 03:07:37 +00:00
AlphaInstrInfo.td catch constants more often 2006-09-20 15:05:49 +00:00
AlphaJITInfo.cpp Resolve BB references with relocation. 2006-07-27 18:21:10 +00:00
AlphaJITInfo.h Completely rearchitect the interface between targets and the pass manager. 2006-09-04 04:14:57 +00:00
AlphaLLRP.cpp Account for pseudo-ops correctly 2006-09-20 20:08:52 +00:00
AlphaRegisterInfo.cpp Completely eliminate def&use operands. Now a register operand is EITHER a 2006-09-05 02:31:13 +00:00
AlphaRegisterInfo.h getCalleeSaveRegs and getCalleeSaveRegClasses are no long TableGen'd. 2006-05-18 00:12:58 +00:00
AlphaRegisterInfo.td Constify some methods. Patch provided by Anton Vayvod, thanks! 2006-08-17 22:00:08 +00:00
AlphaRelocations.h Patches to make the LLVM sources more -pedantic clean. Patch provided 2006-05-24 17:04:05 +00:00
AlphaSchedule.td Alpha Scheduling classes 2006-03-09 17:16:45 +00:00
AlphaSubtarget.cpp Give full control of subtarget features over to table generated code. 2005-10-26 17:30:34 +00:00
AlphaSubtarget.h Alpha Scheduling classes 2006-03-09 17:16:45 +00:00
AlphaTargetAsmInfo.cpp Fix jump tables to match gcc (and the ABI and whatnot) 2006-09-24 19:46:56 +00:00
AlphaTargetAsmInfo.h Break out target asm info into separate files. 2006-09-07 22:05:02 +00:00
AlphaTargetMachine.cpp Fix jump tables to match gcc (and the ABI and whatnot) 2006-09-24 19:46:56 +00:00
AlphaTargetMachine.h 1. Remove condition on delete. 2006-09-07 23:39:26 +00:00
Makefile Autogen subtarget information from .td files. 2005-10-23 22:15:34 +00:00
Readme.txt jump table note 2006-09-24 13:13:10 +00:00

Readme.txt

Fix jump table support.  currently it uses 64bit absolute address. 
gcc uses gprel32.  This way I won't keep fighting Evan as he keeps
breaking 64bit entries in jump tables...

#include <string.h>
#include <setjmp.h>

int main(int x, char** y)
{
char* foo;
switch(x) {
case 1:
foo = "1";
break;
case 2:
foo = "2";
break;
case 3:
foo = "3";
break;
case 4:
foo = "4";
break;
case 5:
foo = "5";
break;
case 6:
foo = "6";
break;
case 7:
foo = "7";
break;
case 8:
foo = "8";
break;
};
print(foo);
return 0;

}


        .set noreorder
        .set volatile
        .set noat
        .set nomacro
        .section        .rodata.str1.1,"aMS",@progbits,1
$LC6:
        .ascii "7\0"
$LC7:
        .ascii "8\0"
$LC0:
        .ascii "1\0"
$LC1:
        .ascii "2\0"
$LC2:
        .ascii "3\0"
$LC3:
        .ascii "4\0"
$LC4:
        .ascii "5\0"
$LC5:
        .ascii "6\0"
        .text
        .align 2
        .align 4
        .globl main
        .ent main
main:
        .frame $30,16,$26,0
        .mask 0x4000000,-16
        ldah $29,0($27)         !gpdisp!1
        lda $29,0($29)          !gpdisp!1
$main..ng:
        zapnot $16,15,$16
        lda $30,-16($30)
        cmpule $16,8,$1
        stq $26,0($30)
        .prologue 1
        beq $1,$L2
        ldah $6,$L11($29)               !gprelhigh
        lda $5,$L11($6)         !gprellow
        s4addq $16,$5,$0
        ldl $2,0($0)
        addq $29,$2,$3
        jmp $31,($3),$L2
        .section        .rodata
        .align 2
        .align 2
$L11:
        .gprel32 $L2
        .gprel32 $L3
        .gprel32 $L4
        .gprel32 $L5
        .gprel32 $L6
        .gprel32 $L7
        .gprel32 $L8
        .gprel32 $L9
        .gprel32 $L10
        .text
$L9:
        ldah $20,$LC6($29)              !gprelhigh
        lda $4,$LC6($20)                !gprellow
        .align 4
$L2:
        mov $4,$16
        ldq $27,print($29)              !literal!2
        jsr $26,($27),print             !lituse_jsr!2
        ldah $29,0($26)         !gpdisp!3
        mov $31,$0
        bis $31,$31,$31
        lda $29,0($29)          !gpdisp!3
        ldq $26,0($30)
        lda $30,16($30)
        ret $31,($26),1
$L10:
        ldah $21,$LC7($29)              !gprelhigh
        lda $4,$LC7($21)                !gprellow
        br $31,$L2
$L3:
        ldah $7,$LC0($29)               !gprelhigh
        lda $4,$LC0($7)         !gprellow
        br $31,$L2
$L4:
        ldah $8,$LC1($29)               !gprelhigh
        lda $4,$LC1($8)         !gprellow
        br $31,$L2
$L5:
        ldah $16,$LC2($29)              !gprelhigh
        lda $4,$LC2($16)                !gprellow
        br $31,$L2
$L6:
        ldah $17,$LC3($29)              !gprelhigh
        lda $4,$LC3($17)                !gprellow
        br $31,$L2
$L7:
        ldah $18,$LC4($29)              !gprelhigh
        lda $4,$LC4($18)                !gprellow
        br $31,$L2
$L8:
        ldah $19,$LC5($29)              !gprelhigh
        lda $4,$LC5($19)                !gprellow
        br $31,$L2
        .end main
        .section        .note.GNU-stack,"",@progbits
        .ident  "GCC: (GNU) 3.4.4 20050314 (prerelease) (Debian 3.4.3-13)"




%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
Fix Ordered/Unordered FP stuff


%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
improve bytezap opertunities
ulong %foo(ulong %y) {
entry:
        %tmp = and ulong %y,  65535
        %tmp2 = shr ulong %tmp,  ubyte 3
        ret ulong %tmp2
}


compiles to a 3 instruction sequence without instcombine
        zapnot $16,3,$0
        srl $0,3,$0
        ret $31,($26),1
 
After instcombine you get
ulong %foo(ulong %y) {
entry:
        %tmp = shr ulong %y, ubyte 3            ; <ulong> [#uses=1]
        %tmp2 = and ulong %tmp, 8191            ; <ulong> [#uses=1]
        ret ulong %tmp2
}

which compiles to
        lda $0,8191($31)
        srl $16,3,$1
        and $1,$0,$0
        ret $31,($26),1