..
AsmParser
[RISCV] Update V extension to v1.0-draft 08a0b464.
2021-01-26 12:02:43 +08:00
Disassembler
[RISCV] Merge Utils library into MCTargetDesc
2021-01-14 11:47:30 -08:00
MCTargetDesc
[RISCV] Move RISCVVPseudosTable from RISCVBaseInfo.h to RISCVInstrInfo.h. NFC
2021-01-27 13:38:26 -08:00
TargetInfo
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
CMakeLists.txt
[RISCV] Merge Utils library into MCTargetDesc
2021-01-14 11:47:30 -08:00
RISCV.h
[RISCV] Merge Utils library into MCTargetDesc
2021-01-14 11:47:30 -08:00
RISCV.td
[RISCV] Fix name of Zba extension (NFC)
2021-01-24 21:02:34 +00:00
RISCVAsmPrinter.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVCallLowering.cpp
[GlobalISel] Base implementation for sret demotion.
2021-01-06 10:30:50 +05:30
RISCVCallLowering.h
[GlobalISel] Base implementation for sret demotion.
2021-01-06 10:30:50 +05:30
RISCVCallingConv.td
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RISCVCleanupVSETVLI.cpp
[RISCV] Add a pass to remove duplicate VSETVLI instructions in a basic block.
2020-12-11 10:35:37 -08:00
RISCVExpandAtomicPseudoInsts.cpp
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RISCVExpandPseudoInsts.cpp
[RISCV] Define vmclr.m/vmset.m intrinsics.
2020-12-28 18:57:17 -08:00
RISCVFrameLowering.cpp
[RISCV] Do not grow the stack a second time when we need to realign the stack
2021-01-09 16:51:09 +00:00
RISCVFrameLowering.h
[SVE] Return StackOffset for TargetFrameLowering::getFrameIndexReference.
2020-11-05 11:02:18 +00:00
RISCVISelDAGToDAG.cpp
[RISCV] Rework fault first only load isel.
2021-01-27 11:51:41 -08:00
RISCVISelDAGToDAG.h
[RISCV] Implement vlsegff intrinsics.
2021-01-26 12:02:43 +08:00
RISCVISelLowering.cpp
[RISCV] Rework fault first only load isel.
2021-01-27 11:51:41 -08:00
RISCVISelLowering.h
[RISCV] Reduce field sizes in searchable tables to reduce binary size.
2021-01-27 12:24:01 -08:00
RISCVInstrFormats.td
[RISCV] Update V instructions constraints to conform to v1.0
2021-01-22 01:15:55 +08:00
RISCVInstrFormatsC.td
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RISCVInstrFormatsV.td
[RISCV] New vector load/store in V extension v1.0
2021-01-22 07:30:09 +08:00
RISCVInstrInfo.cpp
[RISCV] Move RISCVVPseudosTable from RISCVBaseInfo.h to RISCVInstrInfo.h. NFC
2021-01-27 13:38:26 -08:00
RISCVInstrInfo.h
[RISCV] Move RISCVVPseudosTable from RISCVBaseInfo.h to RISCVInstrInfo.h. NFC
2021-01-27 13:38:26 -08:00
RISCVInstrInfo.td
[RISCV] Add isel patterns to optimize slli.uw patterns without Zba extension.
2021-01-25 16:12:08 -08:00
RISCVInstrInfoA.td
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RISCVInstrInfoB.td
[RISCV] Add isel patterns to optimize slli.uw patterns without Zba extension.
2021-01-25 16:12:08 -08:00
RISCVInstrInfoC.td
[RISCV] Add way to mark CompressPats that should only be used for compressing.
2021-01-20 09:20:15 -08:00
RISCVInstrInfoD.td
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
RISCVInstrInfoF.td
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
RISCVInstrInfoM.td
[RISCV] Don't remove (and X, 0xffffffff) from inputs when matching RISCVISD::DIVUW/REMUW to 64-bit DIVU/REMU.
2020-11-26 23:15:41 -08:00
RISCVInstrInfoV.td
[RISCV] New vector load/store in V extension v1.0
2021-01-22 07:30:09 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Rework fault first only load isel.
2021-01-27 11:51:41 -08:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR.
2021-01-26 01:00:50 -08:00
RISCVInstrInfoZfh.td
[RISCV][LegalizeDAG] Expand SETO and SETUO comparisons. Teach LegalizeDAG to expand SETUO expansion when UNE isn't legal.
2020-12-10 09:15:52 -08:00
RISCVInstructionSelector.cpp
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RISCVLegalizerInfo.cpp
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RISCVLegalizerInfo.h
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RISCVMCInstLower.cpp
[RISCV] Define different pseudo instructions for different FPR.
2021-01-26 15:48:35 +08:00
RISCVMachineFunctionInfo.h
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RISCVMergeBaseOffset.cpp
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00
RISCVRegisterBankInfo.cpp
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RISCVRegisterBankInfo.h
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RISCVRegisterBanks.td
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RISCVRegisterInfo.cpp
[RISCV] Define the remaining vector fixed-point arithmetic intrinsics.
2020-12-20 22:57:07 -08:00
RISCVRegisterInfo.h
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RISCVRegisterInfo.td
[RISCV] Correct DWARF number for vector registers.
2021-01-22 11:33:42 +08:00
RISCVSchedRocket.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSchedSiFive7.td
[RISCV] Use the commercial name for scheduling model (NFC)
2020-10-23 16:33:27 -05:00
RISCVSchedule.td
[RISCV] Fix formatting (NFC)
2020-09-25 18:15:04 -05:00
RISCVSubtarget.cpp
[RISCV] Add -mtune support
2020-10-16 13:55:08 +08:00
RISCVSubtarget.h
[RISCV] Add Zba feature and move add.uw and slli.uw to it.
2021-01-22 12:49:10 -08:00
RISCVSystemOperands.td
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RISCVTargetMachine.cpp
[RISCV] Merge Utils library into MCTargetDesc
2021-01-14 11:47:30 -08:00
RISCVTargetMachine.h
[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.
2020-12-18 21:50:55 +00:00
RISCVTargetObjectFile.cpp
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RISCVTargetObjectFile.h
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RISCVTargetTransformInfo.cpp
[RISCV] Merge Utils library into MCTargetDesc
2021-01-14 11:47:30 -08:00
RISCVTargetTransformInfo.h
[ARM][TTI] Prevents constants in a min(max) or max(min) pattern from being hoisted when in a loop
2020-09-22 11:54:10 +00:00
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