forked from OSchip/llvm-project
43 lines
1.6 KiB
TableGen
43 lines
1.6 KiB
TableGen
//===-- enums.td - EnumsGen test definition file -----------*- tablegen -*-===//
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//
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// Copyright 2019 The MLIR Authors.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// =============================================================================
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include "mlir/IR/OpBase.td"
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def CaseA: StrEnumAttrCase<"CaseA">;
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def CaseB: StrEnumAttrCase<"CaseB", 10>;
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def StrEnum: StrEnumAttr<"StrEnum", "A test enum", [CaseA, CaseB]> {
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let cppNamespace = "Outer::Inner";
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let stringToSymbolFnName = "ConvertToEnum";
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let symbolToStringFnName = "ConvertToString";
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}
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def Case5: I32EnumAttrCase<"Case5", 5>;
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def Case10: I32EnumAttrCase<"Case10", 10>;
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def I32Enum: I32EnumAttr<"I32Enum", "A test enum", [Case5, Case10]>;
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def Bit0 : BitEnumAttrCase<"None", 0x0000>;
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def Bit1 : BitEnumAttrCase<"Bit1", 0x0001>;
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def Bit3 : BitEnumAttrCase<"Bit3", 0x0004>;
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def BitEnumWithNone : BitEnumAttr<"BitEnumWithNone", "A test enum",
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[Bit0, Bit1, Bit3]>;
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def BitEnumWithoutNone : BitEnumAttr<"BitEnumWithoutNone", "A test enum",
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[Bit1, Bit3]>;
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