forked from OSchip/llvm-project
542 lines
20 KiB
C++
542 lines
20 KiB
C++
//=- WebAssemblyISelLowering.cpp - WebAssembly DAG Lowering Implementation -==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file implements the WebAssemblyTargetLowering class.
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///
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//===----------------------------------------------------------------------===//
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#include "WebAssemblyISelLowering.h"
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#include "MCTargetDesc/WebAssemblyMCTargetDesc.h"
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#include "WebAssemblyMachineFunctionInfo.h"
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#include "WebAssemblySubtarget.h"
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#include "WebAssemblyTargetMachine.h"
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#include "WebAssemblyTargetObjectFile.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineJumpTableInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/DiagnosticInfo.h"
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#include "llvm/IR/DiagnosticPrinter.h"
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#include "llvm/IR/Function.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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#define DEBUG_TYPE "wasm-lower"
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namespace {
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// Diagnostic information for unimplemented or unsupported feature reporting.
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// TODO: This code is copied from BPF and AMDGPU; consider factoring it out
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// and sharing code.
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class DiagnosticInfoUnsupported final : public DiagnosticInfo {
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private:
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// Debug location where this diagnostic is triggered.
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DebugLoc DLoc;
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const Twine &Description;
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const Function &Fn;
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SDValue Value;
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static int KindID;
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static int getKindID() {
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if (KindID == 0)
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KindID = llvm::getNextAvailablePluginDiagnosticKind();
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return KindID;
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}
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public:
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DiagnosticInfoUnsupported(SDLoc DLoc, const Function &Fn, const Twine &Desc,
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SDValue Value)
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: DiagnosticInfo(getKindID(), DS_Error), DLoc(DLoc.getDebugLoc()),
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Description(Desc), Fn(Fn), Value(Value) {}
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void print(DiagnosticPrinter &DP) const override {
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std::string Str;
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raw_string_ostream OS(Str);
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if (DLoc) {
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auto DIL = DLoc.get();
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StringRef Filename = DIL->getFilename();
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unsigned Line = DIL->getLine();
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unsigned Column = DIL->getColumn();
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OS << Filename << ':' << Line << ':' << Column << ' ';
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}
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OS << "in function " << Fn.getName() << ' ' << *Fn.getFunctionType() << '\n'
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<< Description;
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if (Value)
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Value->print(OS);
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OS << '\n';
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OS.flush();
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DP << Str;
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}
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static bool classof(const DiagnosticInfo *DI) {
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return DI->getKind() == getKindID();
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}
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};
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int DiagnosticInfoUnsupported::KindID = 0;
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} // end anonymous namespace
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WebAssemblyTargetLowering::WebAssemblyTargetLowering(
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const TargetMachine &TM, const WebAssemblySubtarget &STI)
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: TargetLowering(TM), Subtarget(&STI) {
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auto MVTPtr = Subtarget->hasAddr64() ? MVT::i64 : MVT::i32;
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// Booleans always contain 0 or 1.
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setBooleanContents(ZeroOrOneBooleanContent);
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// WebAssembly does not produce floating-point exceptions on normal floating
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// point operations.
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setHasFloatingPointExceptions(false);
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// We don't know the microarchitecture here, so just reduce register pressure.
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setSchedulingPreference(Sched::RegPressure);
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// Tell ISel that we have a stack pointer.
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setStackPointerRegisterToSaveRestore(
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Subtarget->hasAddr64() ? WebAssembly::SP64 : WebAssembly::SP32);
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// Set up the register classes.
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addRegisterClass(MVT::i32, &WebAssembly::I32RegClass);
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addRegisterClass(MVT::i64, &WebAssembly::I64RegClass);
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addRegisterClass(MVT::f32, &WebAssembly::F32RegClass);
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addRegisterClass(MVT::f64, &WebAssembly::F64RegClass);
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// Compute derived properties from the register classes.
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computeRegisterProperties(Subtarget->getRegisterInfo());
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setOperationAction(ISD::GlobalAddress, MVTPtr, Custom);
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setOperationAction(ISD::ExternalSymbol, MVTPtr, Custom);
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setOperationAction(ISD::JumpTable, MVTPtr, Custom);
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for (auto T : {MVT::f32, MVT::f64}) {
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// Don't expand the floating-point types to constant pools.
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setOperationAction(ISD::ConstantFP, T, Legal);
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// Expand floating-point comparisons.
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for (auto CC : {ISD::SETO, ISD::SETUO, ISD::SETUEQ, ISD::SETONE,
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ISD::SETULT, ISD::SETULE, ISD::SETUGT, ISD::SETUGE})
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setCondCodeAction(CC, T, Expand);
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// Expand floating-point library function operators.
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for (auto Op : {ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOWI, ISD::FPOW})
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setOperationAction(Op, T, Expand);
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// Note supported floating-point library function operators that otherwise
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// default to expand.
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for (auto Op :
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{ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FNEARBYINT, ISD::FRINT})
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setOperationAction(Op, T, Legal);
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// Support minnan and maxnan, which otherwise default to expand.
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setOperationAction(ISD::FMINNAN, T, Legal);
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setOperationAction(ISD::FMAXNAN, T, Legal);
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}
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for (auto T : {MVT::i32, MVT::i64}) {
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// Expand unavailable integer operations.
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for (auto Op :
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{ISD::BSWAP, ISD::ROTL, ISD::ROTR, ISD::SMUL_LOHI, ISD::UMUL_LOHI,
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ISD::MULHS, ISD::MULHU, ISD::SDIVREM, ISD::UDIVREM, ISD::SHL_PARTS,
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ISD::SRA_PARTS, ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC,
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ISD::SUBE}) {
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setOperationAction(Op, T, Expand);
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}
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}
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// As a special case, these operators use the type to mean the type to
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// sign-extend from.
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for (auto T : {MVT::i1, MVT::i8, MVT::i16})
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setOperationAction(ISD::SIGN_EXTEND_INREG, T, Expand);
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// Dynamic stack allocation: use the default expansion.
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVTPtr, Expand);
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// Expand these forms; we pattern-match the forms that we can handle in isel.
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for (auto T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64})
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for (auto Op : {ISD::BR_CC, ISD::SELECT_CC})
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setOperationAction(Op, T, Expand);
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// We have custom switch handling.
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setOperationAction(ISD::BR_JT, MVT::Other, Custom);
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// WebAssembly doesn't have:
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// - Floating-point extending loads.
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// - Floating-point truncating stores.
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// - i1 extending loads.
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f64, Expand);
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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for (auto T : MVT::integer_valuetypes())
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for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
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setLoadExtAction(Ext, T, MVT::i1, Promote);
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// Trap lowers to wasm unreachable
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setOperationAction(ISD::TRAP, MVT::Other, Legal);
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}
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FastISel *WebAssemblyTargetLowering::createFastISel(
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FunctionLoweringInfo &FuncInfo, const TargetLibraryInfo *LibInfo) const {
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return WebAssembly::createFastISel(FuncInfo, LibInfo);
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}
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bool WebAssemblyTargetLowering::isOffsetFoldingLegal(
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const GlobalAddressSDNode * /*GA*/) const {
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// The WebAssembly target doesn't support folding offsets into global
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// addresses.
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return false;
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}
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MVT WebAssemblyTargetLowering::getScalarShiftAmountTy(const DataLayout & /*DL*/,
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EVT VT) const {
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return VT.getSimpleVT();
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}
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const char *
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WebAssemblyTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (static_cast<WebAssemblyISD::NodeType>(Opcode)) {
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case WebAssemblyISD::FIRST_NUMBER:
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break;
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#define HANDLE_NODETYPE(NODE) \
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case WebAssemblyISD::NODE: \
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return "WebAssemblyISD::" #NODE;
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#include "WebAssemblyISD.def"
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#undef HANDLE_NODETYPE
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}
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return nullptr;
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}
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std::pair<unsigned, const TargetRegisterClass *>
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WebAssemblyTargetLowering::getRegForInlineAsmConstraint(
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const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
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// First, see if this is a constraint that directly corresponds to a
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// WebAssembly register class.
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if (Constraint.size() == 1) {
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switch (Constraint[0]) {
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case 'r':
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if (VT == MVT::i32)
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return std::make_pair(0U, &WebAssembly::I32RegClass);
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if (VT == MVT::i64)
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return std::make_pair(0U, &WebAssembly::I64RegClass);
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break;
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default:
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break;
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}
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}
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return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
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}
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bool WebAssemblyTargetLowering::isCheapToSpeculateCttz() const {
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// Assume ctz is a relatively cheap operation.
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return true;
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}
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bool WebAssemblyTargetLowering::isCheapToSpeculateCtlz() const {
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// Assume clz is a relatively cheap operation.
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return true;
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}
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//===----------------------------------------------------------------------===//
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// WebAssembly Lowering private implementation.
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Lowering Code
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//===----------------------------------------------------------------------===//
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static void fail(SDLoc DL, SelectionDAG &DAG, const char *msg) {
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MachineFunction &MF = DAG.getMachineFunction();
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DAG.getContext()->diagnose(
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DiagnosticInfoUnsupported(DL, *MF.getFunction(), msg, SDValue()));
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}
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// Test whether the given calling convention is supported.
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static bool CallingConvSupported(CallingConv::ID CallConv) {
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// We currently support the language-independent target-independent
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// conventions. We don't yet have a way to annotate calls with properties like
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// "cold", and we don't have any call-clobbered registers, so these are mostly
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// all handled the same.
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return CallConv == CallingConv::C || CallConv == CallingConv::Fast ||
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CallConv == CallingConv::Cold ||
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CallConv == CallingConv::PreserveMost ||
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CallConv == CallingConv::PreserveAll ||
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CallConv == CallingConv::CXX_FAST_TLS;
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}
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SDValue
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WebAssemblyTargetLowering::LowerCall(CallLoweringInfo &CLI,
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SmallVectorImpl<SDValue> &InVals) const {
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SelectionDAG &DAG = CLI.DAG;
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SDLoc DL = CLI.DL;
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SDValue Chain = CLI.Chain;
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SDValue Callee = CLI.Callee;
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MachineFunction &MF = DAG.getMachineFunction();
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CallingConv::ID CallConv = CLI.CallConv;
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if (!CallingConvSupported(CallConv))
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fail(DL, DAG,
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"WebAssembly doesn't support language-specific or target-specific "
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"calling conventions yet");
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if (CLI.IsPatchPoint)
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fail(DL, DAG, "WebAssembly doesn't support patch point yet");
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// WebAssembly doesn't currently support explicit tail calls. If they are
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// required, fail. Otherwise, just disable them.
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if ((CallConv == CallingConv::Fast && CLI.IsTailCall &&
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MF.getTarget().Options.GuaranteedTailCallOpt) ||
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(CLI.CS && CLI.CS->isMustTailCall()))
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fail(DL, DAG, "WebAssembly doesn't support tail call yet");
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CLI.IsTailCall = false;
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SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
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SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
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if (Ins.size() > 1)
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fail(DL, DAG, "WebAssembly doesn't support more than 1 returned value yet");
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SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
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for (const ISD::OutputArg &Out : Outs) {
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assert(!Out.Flags.isByVal() && "byval is not valid for return values");
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assert(!Out.Flags.isNest() && "nest is not valid for return values");
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if (Out.Flags.isInAlloca())
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fail(DL, DAG, "WebAssembly hasn't implemented inalloca results");
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if (Out.Flags.isInConsecutiveRegs())
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fail(DL, DAG, "WebAssembly hasn't implemented cons regs results");
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if (Out.Flags.isInConsecutiveRegsLast())
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fail(DL, DAG, "WebAssembly hasn't implemented cons regs last results");
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}
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bool IsVarArg = CLI.IsVarArg;
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if (IsVarArg)
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fail(DL, DAG, "WebAssembly doesn't support varargs yet");
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// Analyze operands of the call, assigning locations to each operand.
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
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unsigned NumBytes = CCInfo.getNextStackOffset();
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auto PtrVT = getPointerTy(MF.getDataLayout());
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auto Zero = DAG.getConstant(0, DL, PtrVT, true);
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auto NB = DAG.getConstant(NumBytes, DL, PtrVT, true);
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Chain = DAG.getCALLSEQ_START(Chain, NB, DL);
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SmallVector<SDValue, 16> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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Ops.append(OutVals.begin(), OutVals.end());
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SmallVector<EVT, 8> Tys;
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for (const auto &In : Ins) {
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if (In.Flags.isByVal())
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fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
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if (In.Flags.isInAlloca())
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fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
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if (In.Flags.isNest())
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fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
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if (In.Flags.isInConsecutiveRegs())
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fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
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if (In.Flags.isInConsecutiveRegsLast())
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fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
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// Ignore In.getOrigAlign() because all our arguments are passed in
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// registers.
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Tys.push_back(In.VT);
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}
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Tys.push_back(MVT::Other);
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SDVTList TyList = DAG.getVTList(Tys);
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SDValue Res =
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DAG.getNode(Ins.empty() ? WebAssemblyISD::CALL0 : WebAssemblyISD::CALL1,
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DL, TyList, Ops);
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if (Ins.empty()) {
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Chain = Res;
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} else {
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InVals.push_back(Res);
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Chain = Res.getValue(1);
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}
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Chain = DAG.getCALLSEQ_END(Chain, NB, Zero, SDValue(), DL);
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return Chain;
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}
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bool WebAssemblyTargetLowering::CanLowerReturn(
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CallingConv::ID /*CallConv*/, MachineFunction & /*MF*/, bool /*IsVarArg*/,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext & /*Context*/) const {
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// WebAssembly can't currently handle returning tuples.
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return Outs.size() <= 1;
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}
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SDValue WebAssemblyTargetLowering::LowerReturn(
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SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals, SDLoc DL,
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SelectionDAG &DAG) const {
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assert(Outs.size() <= 1 && "WebAssembly can only return up to one value");
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if (!CallingConvSupported(CallConv))
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fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
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if (IsVarArg)
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fail(DL, DAG, "WebAssembly doesn't support varargs yet");
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SmallVector<SDValue, 4> RetOps(1, Chain);
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RetOps.append(OutVals.begin(), OutVals.end());
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Chain = DAG.getNode(WebAssemblyISD::RETURN, DL, MVT::Other, RetOps);
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// Record the number and types of the return values.
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for (const ISD::OutputArg &Out : Outs) {
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assert(!Out.Flags.isByVal() && "byval is not valid for return values");
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assert(!Out.Flags.isNest() && "nest is not valid for return values");
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if (Out.Flags.isInAlloca())
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fail(DL, DAG, "WebAssembly hasn't implemented inalloca results");
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if (Out.Flags.isInConsecutiveRegs())
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fail(DL, DAG, "WebAssembly hasn't implemented cons regs results");
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if (Out.Flags.isInConsecutiveRegsLast())
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fail(DL, DAG, "WebAssembly hasn't implemented cons regs last results");
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if (!Out.IsFixed)
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fail(DL, DAG, "WebAssembly doesn't support non-fixed results yet");
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}
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return Chain;
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}
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SDValue WebAssemblyTargetLowering::LowerFormalArguments(
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SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
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const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc DL, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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MachineFunction &MF = DAG.getMachineFunction();
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if (!CallingConvSupported(CallConv))
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fail(DL, DAG, "WebAssembly doesn't support non-C calling conventions");
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if (IsVarArg)
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fail(DL, DAG, "WebAssembly doesn't support varargs yet");
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// Set up the incoming ARGUMENTS value, which serves to represent the liveness
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// of the incoming values before they're represented by virtual registers.
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MF.getRegInfo().addLiveIn(WebAssembly::ARGUMENTS);
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for (const ISD::InputArg &In : Ins) {
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if (In.Flags.isByVal())
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fail(DL, DAG, "WebAssembly hasn't implemented byval arguments");
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if (In.Flags.isInAlloca())
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fail(DL, DAG, "WebAssembly hasn't implemented inalloca arguments");
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if (In.Flags.isNest())
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fail(DL, DAG, "WebAssembly hasn't implemented nest arguments");
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if (In.Flags.isInConsecutiveRegs())
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fail(DL, DAG, "WebAssembly hasn't implemented cons regs arguments");
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if (In.Flags.isInConsecutiveRegsLast())
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fail(DL, DAG, "WebAssembly hasn't implemented cons regs last arguments");
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// Ignore In.getOrigAlign() because all our arguments are passed in
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// registers.
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InVals.push_back(
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In.Used
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? DAG.getNode(WebAssemblyISD::ARGUMENT, DL, In.VT,
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DAG.getTargetConstant(InVals.size(), DL, MVT::i32))
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: DAG.getUNDEF(In.VT));
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// Record the number and types of arguments.
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MF.getInfo<WebAssemblyFunctionInfo>()->addParam(In.VT);
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}
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return Chain;
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}
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//===----------------------------------------------------------------------===//
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// Custom lowering hooks.
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//===----------------------------------------------------------------------===//
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SDValue WebAssemblyTargetLowering::LowerOperation(SDValue Op,
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SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default:
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llvm_unreachable("unimplemented operation lowering");
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return SDValue();
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case ISD::GlobalAddress:
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return LowerGlobalAddress(Op, DAG);
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case ISD::ExternalSymbol:
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return LowerExternalSymbol(Op, DAG);
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case ISD::JumpTable:
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return LowerJumpTable(Op, DAG);
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case ISD::BR_JT:
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return LowerBR_JT(Op, DAG);
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}
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}
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|
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SDValue WebAssemblyTargetLowering::LowerGlobalAddress(SDValue Op,
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SelectionDAG &DAG) const {
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SDLoc DL(Op);
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const auto *GA = cast<GlobalAddressSDNode>(Op);
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EVT VT = Op.getValueType();
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assert(GA->getOffset() == 0 &&
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"offsets on global addresses are forbidden by isOffsetFoldingLegal");
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assert(GA->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
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if (GA->getAddressSpace() != 0)
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fail(DL, DAG, "WebAssembly only expects the 0 address space");
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return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
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DAG.getTargetGlobalAddress(GA->getGlobal(), DL, VT));
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|
}
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|
|
|
SDValue
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|
WebAssemblyTargetLowering::LowerExternalSymbol(SDValue Op,
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|
SelectionDAG &DAG) const {
|
|
SDLoc DL(Op);
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|
const auto *ES = cast<ExternalSymbolSDNode>(Op);
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|
EVT VT = Op.getValueType();
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|
assert(ES->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
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return DAG.getNode(WebAssemblyISD::Wrapper, DL, VT,
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DAG.getTargetExternalSymbol(ES->getSymbol(), VT));
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|
}
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|
|
|
SDValue WebAssemblyTargetLowering::LowerJumpTable(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
// There's no need for a Wrapper node because we always incorporate a jump
|
|
// table operand into a TABLESWITCH instruction, rather than ever
|
|
// materializing it in a register.
|
|
const JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
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|
return DAG.getTargetJumpTable(JT->getIndex(), Op.getValueType(),
|
|
JT->getTargetFlags());
|
|
}
|
|
|
|
SDValue WebAssemblyTargetLowering::LowerBR_JT(SDValue Op,
|
|
SelectionDAG &DAG) const {
|
|
SDLoc DL(Op);
|
|
SDValue Chain = Op.getOperand(0);
|
|
const auto *JT = cast<JumpTableSDNode>(Op.getOperand(1));
|
|
SDValue Index = Op.getOperand(2);
|
|
assert(JT->getTargetFlags() == 0 && "WebAssembly doesn't set target flags");
|
|
|
|
SmallVector<SDValue, 8> Ops;
|
|
Ops.push_back(Chain);
|
|
Ops.push_back(Index);
|
|
|
|
MachineJumpTableInfo *MJTI = DAG.getMachineFunction().getJumpTableInfo();
|
|
const auto &MBBs = MJTI->getJumpTables()[JT->getIndex()].MBBs;
|
|
|
|
// TODO: For now, we just pick something arbitrary for a default case for now.
|
|
// We really want to sniff out the guard and put in the real default case (and
|
|
// delete the guard).
|
|
Ops.push_back(DAG.getBasicBlock(MBBs[0]));
|
|
|
|
// Add an operand for each case.
|
|
for (auto MBB : MBBs)
|
|
Ops.push_back(DAG.getBasicBlock(MBB));
|
|
|
|
return DAG.getNode(WebAssemblyISD::TABLESWITCH, DL, MVT::Other, Ops);
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// WebAssembly Optimization Hooks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
MCSection *WebAssemblyTargetObjectFile::SelectSectionForGlobal(
|
|
const GlobalValue *GV, SectionKind /*Kind*/, Mangler & /*Mang*/,
|
|
const TargetMachine & /*TM*/) const {
|
|
// TODO: Be more sophisticated than this.
|
|
return isa<Function>(GV) ? getTextSection() : getDataSection();
|
|
}
|