llvm-project/llvm/test/CodeGen
Alex Richardson b5f69e234e Handle BUNDLE instructions in MipsAsmPrinter
Summary:
In our CHERI fork we use BUNDLE instructions to ensure that a
three-instruction sequence to generate a program-counter-relative value is
emitted without reordering or insertions (since that would break the 32-bit
offset computation).

Currently MipsAsmPrinter asserts when it encounters a pseudo instruction.
To handle BUNDLE we can simply skip the instruction which will then make
EmitInstruction() process the contents of the bundle in order.

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: merge_guards_bot, sdardis, hiraditya, jrtc27, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D70945
2019-12-04 11:30:00 +00:00
..
AArch64 [MacroFusion] Limit the max fused number as 2 to reduce the dependency 2019-12-04 05:05:35 +00:00
AMDGPU AMDGPU: Avoid folding 2 constant operands into an SALU operation 2019-12-04 10:25:34 +00:00
ARC
ARM [GlobalISel]: Allow targets to override how to widen constants during legalization 2019-12-03 10:41:10 -08:00
AVR
BPF [BPF] add "llvm." prefix to BPF internally created globals 2019-11-25 21:34:46 -08:00
Generic [CodeGen] [ExpandReduction] Fix the bug for ExpandReduction() when vector size isn't power of 2 2019-11-02 23:59:12 -04:00
Hexagon [ModuloSchedule] Fix a bug in experimental expander 2019-11-23 16:01:47 -08:00
Inputs
Lanai
MIR [MIRNamer]: Make the check lines in the test robust with regex. 2019-11-16 22:58:45 -08:00
MSP430 [TargetLowering][DAGCombine][MSP430] Shift Amount Threshold in DAGCombine (4) 2019-11-13 09:23:08 +01:00
Mips Handle BUNDLE instructions in MipsAsmPrinter 2019-12-04 11:30:00 +00:00
NVPTX [NVPTX] Added llvm.nvvm.mma.m8n8k4.* intrinsics 2019-10-28 13:55:30 -07:00
PowerPC [PowerPC] folding rlwinm + rlwinm to rlwinm 2019-12-03 21:51:19 -05:00
RISCV [RISCV] Don't force Local Exec TLS for non-PIC 2019-12-03 22:04:54 +00:00
SPARC Temporarily run machine-verifier once in test/CodeGen/SPARC/fp128.ll, so that 2019-12-03 11:21:52 +01:00
SystemZ [SelectionDAG] Expand nnan FMINNUM/FMAXNUM to select sequence 2019-12-04 10:32:35 +01:00
Thumb Revert "[ARM] Allocatable Global Register Variables for ARM" 2019-11-29 17:01:05 +00:00
Thumb2 [ARM] Add some VCMP folding and canonicalisation 2019-12-02 19:57:12 +00:00
WebAssembly [WebAssembly] Fix miscompile of select with and 2019-11-15 16:22:01 -08:00
WinCFGuard [WinCFG] Handle constant casts carefully in .gfids emission 2019-11-01 13:32:03 -07:00
WinEH
X86 [X86] Model DAZ and FTZ 2019-12-04 08:22:45 +08:00
XCore