forked from OSchip/llvm-project
5588dbce73
This patch makes the parser
- reject higher vector registers (>=16) in operands where they should not
be accepted.
- accept higher integers (>=16) in vector register operands.
Review: Ulrich Weigand
Differential Revision: https://reviews.llvm.org/D88888
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| .. | ||
| asm-match.s | ||
| directive-insn-vector.s | ||
| directive-insn.s | ||
| fixups-zEC12.s | ||
| fixups.s | ||
| insn-bad-z13.s | ||
| insn-bad-z14.s | ||
| insn-bad-z15.s | ||
| insn-bad-z196.s | ||
| insn-bad-zEC12.s | ||
| insn-bad.s | ||
| insn-good-z13.s | ||
| insn-good-z14.s | ||
| insn-good-z15.s | ||
| insn-good-z196.s | ||
| insn-good-zEC12.s | ||
| insn-good.s | ||
| invalid-instructions-spellcheck.s | ||
| lit.local.cfg | ||
| regs-bad.s | ||
| regs-good.s | ||
| tokens.s | ||
| word.s | ||