llvm-project/llvm/test/MC/Disassembler
Mark Murray 2b6691894a [ARM][AArch64] Adding Neoverse N2 CPU support
Add support for the Neoverse N2 CPU to the ARM and AArch64 backends.

Differential Revision: https://reviews.llvm.org/D91695
2020-11-25 11:42:54 +00:00
..
AArch64 [ARM][AArch64] Adding Neoverse N2 CPU support 2020-11-25 11:42:54 +00:00
AMDGPU [AMDGPU] Set default op_sel_hi on accvgpr read/write 2020-11-10 13:07:29 -08:00
ARC
ARM [ARM] Fix Asm/Disasm of TBB/TBH instructions 2020-07-22 09:31:56 +01:00
Hexagon
Lanai
MSP430
Mips [mips] Add tests to check disassembling of add.ps/mul.ps/sub.ps instructions 2020-11-13 14:31:12 +03:00
PowerPC [PowerPC] Add outer product instructions for MMA 2020-09-30 18:06:49 -05:00
RISCV [RISCV] Implement evaluateBranch 2020-04-09 15:11:55 +01:00
Sparc
SystemZ [SystemZ] Support z15 processor name 2019-09-20 23:04:45 +00:00
WebAssembly [WebAssembly] Renumber SIMD opcodes 2020-05-01 17:20:49 -07:00
X86 [X86] Support Intel avxvnni 2020-10-31 12:39:51 +08:00
XCore