llvm-project/llvm/test/MC
Fangrui Song 25c8fbb3d9 [X86] Don't emit R_X86_64_[REX_]GOTPCRELX for a GOT load with an offset
clang may produce `movl x@GOTPCREL+4(%rip), %eax` when loading the high
32 bits of the address of a global variable in -fpic/-fpie mode.

If assembled by GNU as, the fixup emits R_X86_64_GOTPCRELX with an addend != -4.
The instruction loads from the GOT entry with an offset and thus it is incorrect
to relax the instruction.

This patch does not emit a relaxable relocation for a GOT load with an offset
because R_X86_64_[REX_]GOTPCRELX do not make sense for instructions which cannot
be relaxed.  The result is good enough for LLD to work. GNU ld relaxes
mov+GOTPCREL as well, but it suppresses the relaxation if addend != -4.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D92114
2020-11-30 08:27:31 -08:00
..
AArch64 [ARM][AArch64] Adding Neoverse N2 CPU support 2020-11-25 11:42:54 +00:00
AMDGPU [AMDGPU][MC] Improved diagnostic messages 2020-11-23 16:15:05 +03:00
ARM [ARMAttributeParser] Correctly parse and print Tag_THUMB_ISA_use=3 2020-11-28 12:28:22 -08:00
AVR [AVRInstPrinter] printOperand: support llvm-objdump --print-imm-hex 2020-07-12 08:14:52 -07:00
AsmParser [MC/AsmParser] Fix use of Arm calling convention in target-agnostic test 2020-11-24 22:56:27 +00:00
BPF [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
COFF [test][MC] Use %python in llvm/test/MC/COFF/bigobj.py 2020-10-07 14:03:28 -04:00
Disassembler [ARM][AArch64] Adding Neoverse N2 CPU support 2020-11-25 11:42:54 +00:00
ELF [X86] Don't emit R_X86_64_[REX_]GOTPCRELX for a GOT load with an offset 2020-11-30 08:27:31 -08:00
Hexagon [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
Lanai
MSP430 [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
MachO llvm-dwarfdump: Dump address forms in their encoded length rather than always in 64 bits 2020-10-04 15:48:57 -07:00
Mips [MC][mips] Remove unused check prefixes. NFC 2020-11-13 14:31:13 +03:00
PowerPC [PowerPC] Allow a '%' prefix for registers in CFI directives 2020-11-19 18:19:51 -08:00
RISCV [RISCV] Use register class VR for V instruction operands directly. 2020-11-19 05:59:46 +08:00
Sparc [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
SystemZ [SystemZAsmParser] Treat VR128 separately in ParseDirectiveInsn(). 2020-10-06 14:42:40 +02:00
VE [VE] Add missing BCR format 2020-10-29 23:30:49 +09:00
WebAssembly [MC][WebAssembly] Only emit indirect function table import if needed 2020-11-25 08:38:43 -08:00
X86 [X86] Don't emit R_X86_64_[REX_]GOTPCRELX for a GOT load with an offset 2020-11-30 08:27:31 -08:00