forked from OSchip/llvm-project
165 lines
5.8 KiB
LLVM
165 lines
5.8 KiB
LLVM
; RUN: sed -e 's/SLHATTR/speculative_load_hardening/' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,SLH,NOGISELSLH --dump-input-on-failure
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; RUN: sed -e 's/SLHATTR//' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s --check-prefixes=CHECK,NOSLH,NOGISELNOSLH --dump-input-on-failure
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; RUN: sed -e 's/SLHATTR/speculative_load_hardening/' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,SLH,GISELSLH --dump-input-on-failure
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; RUN sed -e 's/SLHATTR//' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,NOSLH,GISELNOSLH --dump-input-on-failure
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; RUN: sed -e 's/SLHATTR/speculative_load_hardening/' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -fast-isel | FileCheck %s --check-prefixes=CHECK,SLH,NOGISELSLH --dump-input-on-failure
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; RUN: sed -e 's/SLHATTR//' %s | llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -fast-isel | FileCheck %s --check-prefixes=CHECK,NOSLH,NOGISELNOSLH --dump-input-on-failure
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define i32 @f(i8* nocapture readonly %p, i32 %i, i32 %N) local_unnamed_addr SLHATTR {
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; CHECK-LABEL: f
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entry:
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; SLH: cmp sp, #0
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; SLH: csetm x16, ne
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; NOSLH-NOT: cmp sp, #0
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; NOSLH-NOT: csetm x16, ne
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; SLH: mov [[TMPREG:x[0-9]+]], sp
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; SLH: and [[TMPREG]], [[TMPREG]], x16
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; SLH: mov sp, [[TMPREG]]
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; NOSLH-NOT: mov [[TMPREG:x[0-9]+]], sp
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; NOSLH-NOT: and [[TMPREG]], [[TMPREG]], x16
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; NOSLH-NOT: mov sp, [[TMPREG]]
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%call = tail call i32 @tail_callee(i32 %i)
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; SLH: cmp sp, #0
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; SLH: csetm x16, ne
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; NOSLH-NOT: cmp sp, #0
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; NOSLH-NOT: csetm x16, ne
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%cmp = icmp slt i32 %call, %N
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br i1 %cmp, label %if.then, label %return
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; GlobalISel lowers the branch to a b.ne sometimes instead of b.ge as expected..
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; CHECK: b.[[COND:(ge)|(lt)|(ne)]]
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if.then: ; preds = %entry
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; NOSLH-NOT: csel x16, x16, xzr, {{(lt)|(ge)|(eq)}}
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; SLH-DAG: csel x16, x16, xzr, {{(lt)|(ge)|(eq)}}
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%idxprom = sext i32 %i to i64
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%arrayidx = getelementptr inbounds i8, i8* %p, i64 %idxprom
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%0 = load i8, i8* %arrayidx, align 1
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; CHECK-DAG: ldrb [[LOADED:w[0-9]+]],
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%conv = zext i8 %0 to i32
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br label %return
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; SLH-DAG: csel x16, x16, xzr, [[COND]]
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; NOSLH-NOT: csel x16, x16, xzr, [[COND]]
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return: ; preds = %entry, %if.then
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%retval.0 = phi i32 [ %conv, %if.then ], [ 0, %entry ]
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; SLH: mov [[TMPREG:x[0-9]+]], sp
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; SLH: and [[TMPREG]], [[TMPREG]], x16
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; SLH: mov sp, [[TMPREG]]
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; NOSLH-NOT: mov [[TMPREG:x[0-9]+]], sp
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; NOSLH-NOT: and [[TMPREG]], [[TMPREG]], x16
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; NOSLH-NOT: mov sp, [[TMPREG]]
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ret i32 %retval.0
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}
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; Make sure that for a tail call, taint doesn't get put into SP twice.
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define i32 @tail_caller(i32 %a) local_unnamed_addr SLHATTR {
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; CHECK-LABEL: tail_caller:
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; NOGISELSLH: mov [[TMPREG:x[0-9]+]], sp
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; NOGISELSLH: and [[TMPREG]], [[TMPREG]], x16
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; NOGISELSLH: mov sp, [[TMPREG]]
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; NOGISELNOSLH-NOT: mov [[TMPREG:x[0-9]+]], sp
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; NOGISELNOSLH-NOT: and [[TMPREG]], [[TMPREG]], x16
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; NOGISELNOSLH-NOT: mov sp, [[TMPREG]]
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; GISELSLH: mov [[TMPREG:x[0-9]+]], sp
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; GISELSLH: and [[TMPREG]], [[TMPREG]], x16
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; GISELSLH: mov sp, [[TMPREG]]
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; GISELNOSLH-NOT: mov [[TMPREG:x[0-9]+]], sp
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; GISELNOSLH-NOT: and [[TMPREG]], [[TMPREG]], x16
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; GISELNOSLH-NOT: mov sp, [[TMPREG]]
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; GlobalISel doesn't optimize tail calls (yet?), so only check that
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; cross-call taint register setup code is missing if a tail call was
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; actually produced.
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; NOGISELSLH: b tail_callee
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; GISELSLH: bl tail_callee
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; GISELSLH: cmp sp, #0
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; SLH-NOT: cmp sp, #0
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%call = tail call i32 @tail_callee(i32 %a)
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ret i32 %call
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}
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declare i32 @tail_callee(i32) local_unnamed_addr
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; Verify that no cb(n)z/tb(n)z instructions are produced when implementing
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; SLH
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define i32 @compare_branch_zero(i32, i32) SLHATTR {
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; CHECK-LABEL: compare_branch_zero
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%3 = icmp eq i32 %0, 0
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br i1 %3, label %then, label %else
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;SLH-NOT: cb{{n?}}z
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;NOSLH: cb{{n?}}z
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then:
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%4 = sdiv i32 5, %1
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ret i32 %4
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else:
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%5 = sdiv i32 %1, %0
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ret i32 %5
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}
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define i32 @test_branch_zero(i32, i32) SLHATTR {
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; CHECK-LABEL: test_branch_zero
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%3 = and i32 %0, 16
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%4 = icmp eq i32 %3, 0
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br i1 %4, label %then, label %else
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;SLH-NOT: tb{{n?}}z
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;NOSLH: tb{{n?}}z
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then:
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%5 = sdiv i32 5, %1
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ret i32 %5
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else:
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%6 = sdiv i32 %1, %0
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ret i32 %6
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}
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define i32 @landingpad(i32 %l0, i32 %l1) SLHATTR personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
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; CHECK-LABEL: landingpad
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entry:
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; SLH: cmp sp, #0
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; SLH: csetm x16, ne
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; NOSLH-NOT: cmp sp, #0
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; NOSLH-NOT: csetm x16, ne
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; CHECK: bl _Z10throwing_fv
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invoke void @_Z10throwing_fv()
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to label %exit unwind label %lpad
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; SLH: cmp sp, #0
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; SLH: csetm x16, ne
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lpad:
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%l4 = landingpad { i8*, i32 }
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catch i8* null
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; SLH: cmp sp, #0
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; SLH: csetm x16, ne
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; NOSLH-NOT: cmp sp, #0
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; NOSLH-NOT: csetm x16, ne
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%l5 = extractvalue { i8*, i32 } %l4, 0
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%l6 = tail call i8* @__cxa_begin_catch(i8* %l5)
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%l7 = icmp sgt i32 %l0, %l1
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br i1 %l7, label %then, label %else
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; GlobalISel lowers the branch to a b.ne sometimes instead of b.ge as expected..
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; CHECK: b.[[COND:(le)|(gt)|(ne)]]
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then:
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; SLH-DAG: csel x16, x16, xzr, [[COND]]
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%l9 = sdiv i32 %l0, %l1
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br label %postif
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else:
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; SLH-DAG: csel x16, x16, xzr, {{(gt)|(le)|(eq)}}
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%l11 = sdiv i32 %l1, %l0
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br label %postif
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postif:
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%l13 = phi i32 [ %l9, %then ], [ %l11, %else ]
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tail call void @__cxa_end_catch()
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br label %exit
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exit:
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%l15 = phi i32 [ %l13, %postif ], [ 0, %entry ]
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ret i32 %l15
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}
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declare i32 @__gxx_personality_v0(...)
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declare void @_Z10throwing_fv() local_unnamed_addr
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declare i8* @__cxa_begin_catch(i8*) local_unnamed_addr
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declare void @__cxa_end_catch() local_unnamed_addr
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