llvm-project/llvm/lib/Target/Sparc
Rafael Espindola f8b27c41e8 Nuke the old JIT.
I am sure we will be finding bits and pieces of dead code for years to
come, but this is a good start.

Thanks to Lang Hames for making MCJIT a good replacement!

llvm-svn: 215111
2014-08-07 14:21:18 +00:00
..
AsmParser Replace some assert(0)'s with llvm_unreachable. 2014-06-18 05:05:13 +00:00
Disassembler Prune dependency to MC from each target disassembler. 2014-07-24 11:45:11 +00:00
InstPrinter Convert some assert(0) to llvm_unreachable or fold an 'if' condition into the assert. 2014-06-19 06:10:58 +00:00
MCTargetDesc Use the integrated assembler by default on OpenBSD. 2014-07-10 22:37:28 +00:00
TargetInfo Prune redundant dependencies in LLVMBuild.txt. 2013-12-11 00:30:57 +00:00
CMakeLists.txt Nuke the old JIT. 2014-08-07 14:21:18 +00:00
DelaySlotFiller.cpp Remove the TargetMachine forwards for TargetSubtargetInfo based 2014-08-04 21:25:23 +00:00
LLVMBuild.txt [Sparc] Add initial implementation of disassembler for sparc 2014-01-06 08:08:58 +00:00
Makefile Nuke the old JIT. 2014-08-07 14:21:18 +00:00
README.txt Sparc: No functionality change. Cleanup whitespaces, comment formatting etc., 2013-06-04 18:33:25 +00:00
Sparc.h Nuke the old JIT. 2014-08-07 14:21:18 +00:00
Sparc.td [Sparc] Add VIS instructions to sparc backend. 2014-03-02 19:31:21 +00:00
SparcAsmPrinter.cpp Remove the TargetMachine forwards for TargetSubtargetInfo based 2014-08-04 21:25:23 +00:00
SparcCallingConv.td The SPARCv9 ABI returns a float in %f0. 2014-01-12 04:13:17 +00:00
SparcFrameLowering.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
SparcFrameLowering.h Remove the storage and use of the subtarget out of the sparc frame 2014-06-26 22:33:50 +00:00
SparcISelDAGToDAG.cpp Remove the TargetMachine forwards for TargetSubtargetInfo based 2014-08-04 21:25:23 +00:00
SparcISelLowering.cpp Remove the target machine from CCState. Previously it was only used 2014-08-06 18:45:26 +00:00
SparcISelLowering.h Rename ComputeMaskedBits to computeKnownBits. "Masked" has been 2014-05-14 21:14:37 +00:00
SparcInstr64Bit.td Sparc: disable printing on longer "brX,pt" aliases 2014-05-16 09:41:35 +00:00
SparcInstrAliases.td Sparc: disable printing of jmp/call aliases (C++ does it) 2014-05-16 09:41:39 +00:00
SparcInstrFormats.td [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend. 2014-03-02 23:39:07 +00:00
SparcInstrInfo.cpp [C++] Use 'nullptr'. Target edition. 2014-04-25 05:30:21 +00:00
SparcInstrInfo.h [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Sparc edition 2014-04-29 07:57:13 +00:00
SparcInstrInfo.td Fix a whole bunch of binary literals which were the wrong size. All were being silently zero extended to the correct width. 2014-08-07 05:46:54 +00:00
SparcInstrVIS.td Fix a whole bunch of binary literals which were the wrong size. All were being silently zero extended to the correct width. 2014-08-07 05:46:54 +00:00
SparcMCInstLower.cpp [C++] Use 'nullptr'. Target edition. 2014-04-25 05:30:21 +00:00
SparcMachineFunctionInfo.cpp
SparcMachineFunctionInfo.h [Sparc] Add support for leaf functions in sparc backend. 2013-05-29 04:46:31 +00:00
SparcRegisterInfo.cpp Have MachineFunction cache a pointer to the subtarget to make lookups 2014-08-05 02:39:49 +00:00
SparcRegisterInfo.h [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Sparc edition 2014-04-29 07:57:13 +00:00
SparcRegisterInfo.td [Sparc] Add register class for floating point conditional flags (%fcc0 - %fcc3). 2014-03-02 02:12:33 +00:00
SparcRelocations.h [SparcV9] Add support for JIT in Sparc64. 2014-01-24 07:10:19 +00:00
SparcSelectionDAGInfo.cpp Have SparcSelectionDAGInfo take a DataLayout to initialize since 2014-06-26 22:33:52 +00:00
SparcSelectionDAGInfo.h Have SparcSelectionDAGInfo take a DataLayout to initialize since 2014-06-26 22:33:52 +00:00
SparcSubtarget.cpp Move the various Subtarget dependent members down to the subtarget 2014-06-26 22:33:55 +00:00
SparcSubtarget.h Nuke the old JIT. 2014-08-07 14:21:18 +00:00
SparcTargetMachine.cpp Nuke the old JIT. 2014-08-07 14:21:18 +00:00
SparcTargetMachine.h Nuke the old JIT. 2014-08-07 14:21:18 +00:00
SparcTargetObjectFile.cpp [C++] Use 'nullptr'. Target edition. 2014-04-25 05:30:21 +00:00
SparcTargetObjectFile.h Switch all uses of LLVM_OVERRIDE to just use 'override' directly. 2014-03-02 09:09:27 +00:00
SparcTargetStreamer.h [C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Sparc edition 2014-04-29 07:57:13 +00:00

README.txt

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for
  leaf fns.
* Fill delay slots

* Implement JIT support

* Use %g0 directly to materialize 0. No instruction is required.