forked from OSchip/llvm-project
139 lines
4.1 KiB
C++
139 lines
4.1 KiB
C++
//===- ARMLegalizerInfo.cpp --------------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the Machinelegalizer class for ARM.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "ARMLegalizerInfo.h"
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#include "ARMSubtarget.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Target/TargetOpcodes.h"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "You shouldn't build this"
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#endif
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ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
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using namespace TargetOpcode;
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const LLT p0 = LLT::pointer(0, 32);
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const LLT s1 = LLT::scalar(1);
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const LLT s8 = LLT::scalar(8);
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const LLT s16 = LLT::scalar(16);
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const LLT s32 = LLT::scalar(32);
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const LLT s64 = LLT::scalar(64);
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setAction({G_FRAME_INDEX, p0}, Legal);
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for (unsigned Op : {G_LOAD, G_STORE}) {
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for (auto Ty : {s1, s8, s16, s32, p0})
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setAction({Op, Ty}, Legal);
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setAction({Op, 1, p0}, Legal);
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}
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for (unsigned Op : {G_ADD, G_SUB, G_MUL}) {
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for (auto Ty : {s1, s8, s16})
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setAction({Op, Ty}, WidenScalar);
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setAction({Op, s32}, Legal);
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}
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for (unsigned Op : {G_SDIV, G_UDIV}) {
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for (auto Ty : {s8, s16})
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// FIXME: We need WidenScalar here, but in the case of targets with
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// software division we'll also need Libcall afterwards. Treat as Custom
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// until we have better support for chaining legalization actions.
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setAction({Op, Ty}, Custom);
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if (ST.hasDivideInARMMode())
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setAction({Op, s32}, Legal);
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else
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setAction({Op, s32}, Libcall);
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}
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for (unsigned Op : {G_SEXT, G_ZEXT}) {
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setAction({Op, s32}, Legal);
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for (auto Ty : {s1, s8, s16})
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setAction({Op, 1, Ty}, Legal);
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}
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setAction({G_GEP, p0}, Legal);
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setAction({G_GEP, 1, s32}, Legal);
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setAction({G_CONSTANT, s32}, Legal);
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if (!ST.useSoftFloat() && ST.hasVFP2()) {
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setAction({G_FADD, s32}, Legal);
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setAction({G_FADD, s64}, Legal);
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setAction({G_LOAD, s64}, Legal);
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setAction({G_STORE, s64}, Legal);
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} else {
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for (auto Ty : {s32, s64})
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setAction({G_FADD, Ty}, Libcall);
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}
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for (unsigned Op : {G_FREM, G_FPOW})
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for (auto Ty : {s32, s64})
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setAction({Op, Ty}, Libcall);
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computeTables();
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}
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bool ARMLegalizerInfo::legalizeCustom(MachineInstr &MI,
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MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const {
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using namespace TargetOpcode;
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switch (MI.getOpcode()) {
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default:
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return false;
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case G_SDIV:
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case G_UDIV: {
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LLT Ty = MRI.getType(MI.getOperand(0).getReg());
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if (Ty != LLT::scalar(16) && Ty != LLT::scalar(8))
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return false;
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// We need to widen to 32 bits and then maybe, if the target requires,
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// transform into a libcall.
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LegalizerHelper Helper(MIRBuilder.getMF());
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MachineInstr *NewMI = nullptr;
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Helper.MIRBuilder.recordInsertions([&](MachineInstr *MI) {
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// Store the new, 32-bit div instruction.
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if (MI->getOpcode() == G_SDIV || MI->getOpcode() == G_UDIV)
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NewMI = MI;
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});
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auto Result = Helper.widenScalar(MI, 0, LLT::scalar(32));
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Helper.MIRBuilder.stopRecordingInsertions();
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if (Result == LegalizerHelper::UnableToLegalize) {
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return false;
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}
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assert(NewMI && "Couldn't find widened instruction");
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assert((NewMI->getOpcode() == G_SDIV || NewMI->getOpcode() == G_UDIV) &&
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"Unexpected widened instruction");
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assert(MRI.getType(NewMI->getOperand(0).getReg()).getSizeInBits() == 32 &&
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"Unexpected type for the widened instruction");
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Result = Helper.legalizeInstrStep(*NewMI);
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if (Result == LegalizerHelper::UnableToLegalize) {
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return false;
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}
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return true;
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}
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}
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}
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